Principal CPU Physical Design Engineer (San Diego, CA)
Qualcomm•San Diego, CA
•$211,900 - $317,900•Onsite
About The Position
Drive the Silicon That Powers the Next Generation of Computing. We’re looking for a CPU Physical Design expert to push the limits of performance, power efficiency, and scalability in next-generation CPU designs. In this role, you will work on industry-leading CPU cores at advanced nodes, solving some of the most challenging problems in modern semiconductor design. This is a high-impact role with broad visibility—where your contributions directly influence architecture trade-offs, implementation strategies, and silicon success.
Requirements
- 10+ years of experience in ASIC/SoC Physical Design
- Strong experience with full RTL-to-GDSII implementation (synthesis, place & route, STA, signoff)
- Experience in timing closure and power optimization
- Scripting skills (TCL, Python, or similar)
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 8+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 7+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
- PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
Nice To Haves
- Experience working on CPU cores or other high-performance designs
- Expertise in advanced nodes (7nm, 5nm, 3nm or below)
- Strong understanding of PPA trade-offs and CPU-specific design challenges
- Hands-on experience with industry-standard tools (Synopsys/Cadence)
- Experience developing or influencing design methodologies
- Strong data-driven debug and analytical skills
Responsibilities
- Own critical portions of CPU implementation from RTL to GDS, with a focus on PPA convergence and design quality
- Drive timing, power, and area optimization for high-frequency, complex CPU subsystems
- Partner with Architecture, RTL, and Circuit teams to co-optimize design for physical implementation
- Solve hard silicon problems: timing closure, congestion, variability, EM/IR, and power integrity
- Develop and deploy methodologies, flows, and automation to improve scalability and QoR across projects
- Influence and collaborate with EDA vendors and CAD teams to push tool capabilities
- Contribute to next-gen design strategies for advanced nodes
- Mentor junior engineers and help raise the technical bar of the team
Benefits
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Highly competitive benefits package
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What This Job Offers
Job Type
Full-time
Career Level
Principal
