Principal Collateral Device Engineer

Intel Corporation•Santa Clara, CA

1d•$224,970 - $317,600•Hybrid

About The Position

Intel is transforming from an Integrated Device Manufacturer (IDM) to a leading foundry service provider, offering world-class manufacturing capabilities to customers worldwide. Our Manufacturing Development and Customer Engineering (MDCE) organization is at the forefront of this transformation, focusing on yield improvement, performance optimization, and exceptional customer service delivery. We are seeking a Principal Collateral Device Engineer to join our team within MDCE. This role requires regular onsite presence to fulfill essential job responsibilities and will create next generation device and interconnect technology by ensuring the process device performance for developing processes is world class, using deep understanding of device physics.

Requirements

Master’s degree in Electrical Engineering, Physics, or related field
15+ years of experience in CMOS device engineering with focus on test chip design and device collateral development

Nice To Haves

Ph.D. degree in Electrical Engineering, Physics, or related field
15+ years of experience in CMOS device engineering and collateral development
Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs
Experience with design rule checker (DRC) development and physical verification flows
Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures
Knowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization
Knowledge of mask generation including Boolean/OPC

Responsibilities

Demonstrated expertise in leading cross functional group in defining derivative architectures including Design rules, transistors and interconnects.
Expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture.
Experience in scribe line layout design and process monitoring structure development.
Proficiency in design rule development, validation, and waiver management processes.
Strong understanding of DTCO skills Including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration , Yield, Device and Design.
Strong skills in data analysis, scripting, and statistical techniques for test chip data interpretation.
Excellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs.
Ability to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions.
Demonstrated experience with design of experiment (DOE) principles applied to device collateral optimization.
Proven track record of delivering device collateral solutions in a fast-paced manufacturing environment.
Desire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization.