Principal ASIC Engineer (Reliability & Hardware Validation) Hybrid

Cisco•San Jose, CA

13d•$231,400 - $381,600•Hybrid

About The Position

We are seeking a highly skilled Engineer to lead the reliability and hardware design validation for our next-generation semiconductor and networking products. The ideal candidate will bridge the gap between advanced semiconductor reliability testing and high-speed hardware board design, ensuring our products meet the highest standards of quality, performance, and reliability in hyperscale environments. You will drive innovation by challenging the status quo, transitioning our reliability approach from traditional methods to ground breaking, industry-leading practices. You will act as a primary technical consultant to business leaders, translating sophisticated engineering challenges into clear business value, and lead multi-functional teams through the entire lifecycle—from design FMEA to production qualification.

Requirements

Master’s degree in electrical engineering, Computer Engineering, or a related field.
10+ years of professional experience in semiconductor reliability and/or high-speed hardware design.
Proven experience in developing high-power HTOL/Burn-In testing for advanced node products.
Deep knowledge of JEDEC, AEC, and Telcordia standards.
Hands-on experience with high-speed network interfaces, board design, and familiarity with tools such as Cadence Allegro.
Experience with high-speed measurement equipment and automated test development.
Ability to interpret sophisticated schematics and layouts.
Proficiency in data analysis/debug and HTOL set-up

Nice To Haves

PhD in Electrical or Computer Engineering.
Experience with 2nm/3nm Hyperscaler Multi-Chip-Modules and advanced packaging (CoWoS, SoIC, EMIB).
Deep expertise in >100Gbps system design, signal integrity, and power distribution.
Knowledge of SerDes architecture (NRZ/PAM4 at 56G/112G/224G+), PCIe Gen5/6, and 800G Ethernet.
Proficiency in Python, Perl, TCL, or Verilog for scripting and automation.
Experience with JMP, Reliasoft, or Minitab for reliability statistical analysis.
Understanding of FMEA processes, risk assessment, and reliability lifetime modeling.

Responsibilities

Define and execute comprehensive product/process qualification plans for next-generation, high-power solutions (wafer/package level).
Drive robust, error-free HTOL, Burn-In, and stress testing (HAST, TC, HTS, ESD, LU, SER). Manage reliability suppliers and subcontractors to ensure adherence to qualification schedules.
Lead hardware design, schematic generation, and design validation for service provider routing products. Manage board bring-up and debug processes.
Drive failure analysis activities and generate detailed qualification reports to ensure product integrity.
Partner with eCAD, FPGA, Power, Mechanical, Signal Integrity, and Manufacturing teams to support design-for-reliability and high-speed interface compliance.
Provide technical documentation and support for customer quality and reliability requirements.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
Cisco restricted stock units
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year (non-exempt)
flexible vacation time off program (exempt)
80 hours of sick time off provided on hire date and each January 1st thereafter
up to 80 hours of unused sick time carried forward
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales roles)