Principal ASIC Design Engineer - Chip Lead

CesiumAstro•Aliso Viejo, CA

22d•$15,000 - $199,000

About The Position

Jariet Technologies, Inc., a subsidiary of CesiumAstro, is developing technologies that enable digital communications at micro- and millimeter-wave speeds using standard CMOS processes. Its ASIC products serve emerging markets in multi-antenna beamforming communications systems, wireless infrastructure, microwave point-to-point links, and radar systems. The Principal ASIC Design Engineer will lead next-generation, high-speed mixed-signal and DSP chip projects. The role calls for cradle-to-grave experience across large, high-speed communications chip design, including relevant areas such as digital communications systems, DSP, ASIC microarchitecture, analog IP integration, embedded processors, high-level verification, RTL design across multiple asynchronous clock domains, timing analysis, DFT, backend flow, chip bring-up, debug, lab testing, and transitioning products from first sample through release to volume production. Applicants must meet U.S. Government Space Technology Export Regulations eligibility requirements: be a U.S. citizen, lawful permanent resident, conditional resident, asylee, or refugee, or be eligible to obtain the required U.S. Department of State authorizations.

Requirements

Master’s degree in Engineering and a minimum of 10 years of experience.
Experience with the IC/ASIC development flow from concept through production release of silicon.
Experience defining and using advanced front-end design flows from system simulation through RTL implementation, verification, synthesis, and interfacing with a backend team.
Experience integrating high-speed analog blocks into digital logic.
Ability to analyze specifications at the architecture and microarchitecture levels and identify design improvements.
Excellent program management, people management, and project tracking skills.
Experience with customer communications and marketing or sales interactions.
Experience with ASIC verification using a random constraint coverage-driven methodology such as UVM, VMM, OVM, or SPECMAN.
Fluency with Verilog and SystemVerilog.
Experience with synthesis, formal verification, and STA flow setup.
U.S. Government Space Technology Export Regulations eligibility, as specified in the posting.

Nice To Haves

Experience with low-power design flows.
Experience implementing DSP blocks.

Responsibilities

Lead next-generation high-speed mixed-signal and DSP chip projects.
Work across the ASIC development lifecycle from concept through silicon production release.
Define and use front-end design flows from system simulation through RTL implementation, verification, synthesis, and coordination with a backend team.
Integrate high-speed analog blocks into digital logic.
Analyze specifications at the architecture and microarchitecture levels to identify design improvements.
Manage programs, people, and project tracking.
Participate in customer communications and marketing or sales interactions.
Support chip bring-up, debug, lab testing, and product transition from first sample through volume production.