Principal Applied Scientist, ML Codesign

Amazon • Sunnyvale, CA

5d • $228,700 - $309,400 • Onsite

About The Position

Define the joint optimization of model compression and silicon architecture for Amazon's next generation of edge and cloud inference accelerators. Your work will set the technical targets that propagate across the model, compiler, runtime, and silicon stack. We are hiring a Principal Applied Scientist to be the technical leader who closes the loop between compression science and silicon design. Today's generation ships advanced quantization and large-model distillation in production, running multi-billion parameter language models at inference economics typical of much larger systems. Future generations target significantly larger models at the edge and in the cloud. You will be a principal architect of the next-generation accelerator and of the compression algorithms it executes natively. Few roles in the industry let one technical leader influence the model, the compiler, the runtime, and the silicon without organizational friction. This is one of them. You have spent the last several years thinking about why hardware decisions and accuracy decisions live in different teams, and you want to be the person who owns both. You have published at MLSys, the International Symposium on Computer Architecture (ISCA), the International Symposium on Microarchitecture (MICRO), NeurIPS, or the International Conference on Machine Learning (ICML) on quantization, pruning, or hardware-aware training, and you want your next paper to ship in a chip rather than in a benchmark suite. You want a vertical stack (model, compression, compiler, runtime, operating system, silicon) where the same engineering organization owns every layer and a principal architect can move all of them.

Requirements

• Master's or PhD in Computer Science, Electrical Engineering, or a related field, or equivalent industry experience.
• Eight or more years of industry experience with a track record of first-author or senior-author publications at top-tier venues in machine learning systems, computer architecture, or efficient machine learning.
• Demonstrated experience defining or co-defining a hardware architecture that shipped, including silicon, Field Programmable Gate Array (FPGA), or large-scale software accelerator.
• Deep expertise in at least two of the following: low-bit quantization, structured and unstructured pruning, knowledge distillation, sparse computation, hardware-aware neural architecture search.
• Working knowledge of computer architecture fundamentals: memory hierarchy, dataflow architectures, on-chip interconnect.

Nice To Haves

• Direct experience contributing to silicon architecture for machine learning inference.
• Published work demonstrating hardware-software codesign, where the compression algorithm and the hardware were optimized jointly rather than sequentially.
• Experience applying compression techniques at large-model scale (tens of billions of parameters).
• Familiarity with Application-Specific Integrated Circuit (ASIC) development flow, Register Transfer Level (RTL) review, or compiler intermediate representations including Multi-Level Intermediate Representation (MLIR) and OpenXLA.
• Experience with Mixture-of-Experts (MoE) inference architectures.
• Track record of mentoring senior applied scientists and shaping a multi-year research agenda.
• Prior experience with vertically integrated stacks where the same team owns model, compiler, runtime, and silicon.

Responsibilities

• Define the hardware-aware compression roadmap for next-generation accelerators, working backward from accuracy targets on standard language and reasoning benchmarks including Massive Multitask Language Understanding (MMLU), GSM8K, HumanEval, and Instruction Following Evaluation (IFEval).
• Own the joint optimization of compression algorithms (post-training quantization, quantization-aware training, knowledge distillation, structured pruning) with the underlying hardware.
• Represent applied science in silicon architecture reviews and influence decisions across the memory and compute subsystems of the accelerator.
• Set the science roadmap for the compression techniques the next architecture must support; validate that compression algorithms achieve target accuracy on the benchmarks our products are evaluated against.
• Mentor a team of senior and mid-level applied scientists working on compression and hardware-aware training.
• Serve as a single-threaded technical leader for the codesign agenda, accountable to senior leadership review.

Benefits

• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave
• sign-on payments
• restricted stock units (RSUs)

What This Job Offers

• Job Type: Full-time
• Career Level: Principal