Principal Applications Engineer

Marvell Technology•Santa Clara, CA

6d•$154,680 - $231,700•Hybrid

About The Position

Marvell’s Central Engineering (CE) organization develops the industry’s most advanced High-Speed SerDes (HSS) IPs, covering a broad range of applications including cloud data center, AI/ML infrastructure, 5G wireless, automotive, storage, and optical interconnects. Central System Engineering (CSE), a key function within CE, is responsible for validation, characterization, and application engineering support of high-speed SerDes and analog macros for electrical and optical applications. The team also develops data communication system hardware and software infrastructure to deliver the highest quality SerDes IP and analog macros across Marvell’s Business Units. In this role, you will serve as the primary technical interface between Marvell's Central Engineering IP team and Marvell’s customers, supporting the full lifecycle of SerDes IP integration across customized ASIC and switch programs. This is a hybrid position based on the Santa Clara office, with occasional travel to customer sites for silicon bringup and onsite support.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
Proven experience in high-speed SerDes IP integration and silicon bringup, with a strong foundation in signal integrity analysis, SerDes equalization, and end-to-end debug across complex SoC programs.
Prior work on switch, custom ASIC, or connectivity programs (PCIe, Ethernet, D2D) is highly valued.
The ability to work independently across multiple customer engagements simultaneously, owning the full technical lifecycle from integration kickoff through production.
Strong communication skills are essential.

Responsibilities

Leading SerDes IP integration and customer bringup support from initial design review through silicon validation and production release, including IP kick-off reviews, risk assessments, package and test board reviews, and test plan alignment with internal BUs and customers
Coordinating and driving the right engineering resources across IP design, firmware, and validation teams to ensure smooth SoC bringup and stable production
Diagnosing and resolving signal integrity issues — including equalization, link training, and FEC performance — across multi-data-rate SerDes and supporting analog IPs (analog bias, clock buffers, process monitors, temperature sensors)
Supporting high-speed interface applications including Ethernet single-channel (10G/25G/50G/100G/200G KR/CR/C2M/C2C), PCIe Gen1–Gen6, CPRI, JESD, and CEI
Owning customer technical escalations end-to-end, from root cause analysis through resolution and documentation
Analyzing signal integrity through PCB layout review, channel simulation, and S-parameter analysis to identify integration risks early in the design cycle
Utilizing industry-standard high-speed test equipment — including electrical characterization and compliance test tools — to efficiently isolate and debug issues in the lab
Developing and delivering customer-facing technical collateral including integration guides, application notes, and API documentation
Presenting program status, technical findings, and recommendations to both customer engineering teams and internal leadership
Cross-functional collaboration is central to this role. You will work closely with IP design engineers, DSP and firmware teams, and customer engineers and SoC architects, serving as the technical authority that keeps programs moving forward.