Principal AI System Architect

Credo•San Jose, CA

3d•Onsite

About The Position

Credo is looking for a Principal AI System Architect to join their team. This role focuses on solving system-level interconnection challenges for AI infrastructure, specifically connecting XPUs (NPU/GPU/custom silicon). The architect will define and follow how compute elements are wired, networked, and orchestrated at node, rack, and cluster scales to ensure efficient large-scale LLM training and inference. A strong preference is given to candidates with a hands-on NPU hardware background and experience in deploying NPU silicon into production at scale. The role is based in San Jose, CA, and reports to the AVP, XPU system AI interface.

Requirements

Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field.
Ten years of experience in XPU or AI interconnect system design, architecture, and microarchitecture.
Five cycles of complete ASIC tapeouts.
Strong foundational understanding of computer architecture, including GPU, NPU, and/or CPU design principles.
Deep, hands-on NPU hardware architecture expertise.
Familiarity with large language model architectures and distributed training/inference concepts (e.g., parallelism strategies, model serving) through coursework, research, or personal projects.
Demonstrated analytical ability, for example, through published research, thesis work, or quantitative project work.
Track record of independently studying and synthesizing technical material.
Strong cross-functional leadership and communication skills.
Daily experience working with compiler, software, SOC & backend teams.

Nice To Haves

Master's degree or PhD in a relevant technical field.
Direct NPU tapeout and production ramp experience.
Hands-on NPU hardware background, with direct experience carrying an NPU design from architecture definition through silicon bring-up, validation, and volume production deployment.
Working knowledge of high-speed interconnect or networking concepts (e.g., PCIe, Ethernet, RDMA).

Responsibilities

Solve system-level interconnection challenges that connect XPUs (NPU/GPU/custom silicon) into working AI infrastructure.
Follow and define how compute elements are wired, networked, and orchestrated together at node, rack, and cluster scale.
Ensure large-scale LLM training and inference run efficiently across the platform.