Pre Silicon Verification Engineer

Intel Corporation•Ottawa, ON

4d•CA$109,380 - CA$154,420•Remote

About The Position

Join Intel as a Mixed Signal Design Verification Engineer, where you will play a pivotal role in ensuring the reliability and functionality of cutting-edge mixed signal components that power Intel's advanced technologies. Your expertise will directly contribute to delivering robust designs that meet critical performance, power, and timing goals. As part of a dynamic team, you'll have opportunities to collaborate across diverse architectural and design groups, drive innovation in verification methodologies, and make a tangible impact on Intel's success in the competitive semiconductor landscape.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 1+ years of experience in design verification roles, or a Master's degree with 0+ years of experience
Proficiency in SystemVerilog and Verilog for verification purposes
Demonstrated experience in debugging presilicon issues and implementing corrective actions
Knowledge of scripting languages such as Python for automating verification processes

Nice To Haves

Expertise in OVM and UVM methodologies
Experience in test environment development and planning to ensure coverage and reliability
Familiarity with object-oriented programming (OOP) principles in the context of design verification
Experience leveraging AI-based tools to enhance verification methodologies

Responsibilities

Develop and execute verification plans for mixed signal components, ensuring comprehensive coverage against architectural and microarchitectural specifications
Build and maintain test benches and verification environments to validate functionality, timing, and power requirements
Create analog behavioral models and system simulation models to identify and resolve bugs during the presilicon phase
Replicate, root cause, and debug issues, implementing corrective measures to resolve failures efficiently
Collaborate closely with digital and analog architects, RTL developers, and physical design teams to optimize verification flow and achieve design goals
Perform technical reviews of test plans and proofs with design and architecture teams to ensure accuracy and completeness
Enhance the functional verification infrastructure and methodologies to improve efficiency and reliability
Utilize scripting and advanced tools, including AI-based solutions, to streamline verification flow from test plan generation to test triage