Power and Performance Architect

Intel Corporation•Hillsboro, OR

2d•Hybrid

About The Position

This role operates at the intersection of architecture, technology, and business strategy, influencing Intel’s product roadmaps and key technical tradeoffs across client and server platforms. As a Power and Performance Architect, you will define and optimize system‑level power and performance targets, collaborating closely with IP, SoC, platform, and software engineers using workload‑driven methodologies. The role requires strong system‑level thinking, deep technical judgment, and the ability to lead and influence across organizations while engaging senior technical and executive leadership.

Requirements

B.Sc. / M.Sc. / PhD in Electrical Engineering, Computer Engineering, or a related field with 4+ years of relevant experience in system, SoC, or architectural roles.
Advanced understanding of SoC behavior and power and performance modeling across compute, memory hierarchy, and interconnects.
Experience in workload modeling, workload characterization, or workload abstraction.
Highly self‑motivated, able to operate independently and drive initiatives to completion in ambiguous problem spaces.
Strong problem‑solving skills and attention to detail in modeling assumptions and data quality.
Excellent communication and presentation skills are required to engage senior technical and executive audiences.

Nice To Haves

Experience with Python or scripting languages to develop and maintain analysis tools, flows, and methodologies or modeling frameworks.
Strong understanding of architecture, RTL, structural design (SD), validation, and post‑silicon processes with the ability to reason across abstraction levels.
Experience with Intel IPs and full product development lifecycles.
Expertise in power and performance analysis, system‑level tradeoffs, and power reduction techniques including scalability evaluation.
Hands‑on experience with post‑silicon performance and power measurement, validation, and analysis and correlation back to models.
Background in high‑performance computing, graphics, or AI accelerator workloads.
Experience in semiconductor physics and process technology and their impact on power and performance.
Proven ability to lead complex, cross‑functional technical initiatives with measurable business impact.
Demonstrated success in competitive analysis, market assessment, and long‑term roadmap planning.
Knowledge of business marketing strategies and competitive positioning to inform technical tradeoffs.
Experience in developing and maintaining or institutionalizing analysis tools, flows, and methodologies.

Responsibilities

Drive system‑level PnP projections by defining representative workload models, characterizing workloads, and evaluating architectural trade‑offs across CPU, GPU, memory, fabrics, and platforms.
Develop and own long‑term power and performance models for CPU, GPU, memory IPs, and full SoC and evolve them to support early pathfinding and comparative analysis.
Define power and performance targets and drive execution to achieve aggressive power goals across development phases, from pathfinding to silicon, balancing technology constraints and market requirements.
Develop, maintain, and enhance power and performance modeling tools, flows, and methodologies to enable fast iteration and sensitivity analysis.
Identify emerging technology and market trends, risks, and opportunities impacting competitiveness including evolving workload characteristics.
Provide actionable, data‑driven recommendations to architecture, planning, marketing, and executive leadership that influence product direction and roadmap decisions.
Collaborate cross‑functionally with architecture, design, post‑silicon, platform, and business teams to ensure system‑level power and performance goals are met.