Power Analysis and Optimization Engineer

Advanced Micro Devices, Inc•San Jose, CA

4h•Hybrid

About The Position

AMD-Xilinx is seeking a capable and motivated SoC Design Engineer to be part of Front-End SoC Design Team. In this role, you will focus on power analysis and optimization to help design high performance and power efficient SoCs.

Requirements

Solid background in SoC design with strong knowledge of power reduction techniques.
Proficient in interpreting results from power estimation tools and translating them into effective power optimization strategies.
Strong analytical thinking and problem-solving abilities.
Excellent communication skills, along with the ability to work effectively in a collaborative, team-oriented environment.
Bachelor’s or master’s degree in electrical or computer engineering.

Nice To Haves

SoC/ASIC design background, having participated in several silicon design projects with increasing level of scope/responsibilities in managing power optimization through the project life cycle.
Expertise with low-power design methodologies and trade-offs.
Hands-on expertise with EDA tools such as PrimeTime, PrimePower, Power Artist.
Experience with RTL design and analysis (Verilog/System Verilog).
Experience designing with multiple power domains and islands using UPF.
TCL, Python, Perl scripting, familiarity with AI tools such as Claude, Codex.

Responsibilities

Understand power requirements, establish the baseline, create a strategy to meet requirements, monitor the evolution of the design, and guide the team towards meeting power requirements.
Report status periodically to stake holders.
Perform vector-based and vector-less power estimation for different use case scenarios and analyze results to identify areas for improvement.
Drive static and dynamic power analysis and optimization for complex SoCs and IP blocks.
Drive low-power design strategies.
Power domain/island creation (with UPF).
Develop and maintain power analysis flows using industry-standard EDA tools and emerging, cutting-edge methodologies.
Correlate RTL power estimates with gate-level and post-layout power results.
Contribute to definition/evolution of SoC Design methodologies and processes for future projects.