Post silicon validation engineer
Broadcom•San Jose, CA
•$108,000 - $172,800
About The Position
We are seeking a Post-Silicon Validation Engineer to drive the bring-up, characterization, and debugging of our next-generation Ethernet and PCIe Retimer chips. This role heavily focuses on advanced Ethernet physical layer (PHY) validation, ensuring our silicon meets rigorous IEEE networking standards and high-speed interoperability requirements.
Requirements
- Expertise in Ethernet PHY architecture, PAM4/NRZ signaling, FEC (Forward Error Correction), Auto-Negotiation, and Link Training.
- Proficiency with high-bandwidth Oscilloscopes, BERTs, Ethernet Traffic Generators/Network Analyzers (e.g., Ixia, Spirent), and PCIe Analyzers.
- Strong Python for lab automation and data analysis, plus C/C++ for low-level register manipulation.
- Bachelors in Engineering and 8+ years of related experience or Masters degree in Engineering and 6+ years of related experience
Responsibilities
- Hands-on bring-up of multi-rate Retimer ICs.
- Validate Ethernet (100G/400G/800G) and PCIe (Gen 5/6) for IEEE and PCI-SIG compliance.
- Build Python-based automated test frameworks for Ethernet throughput, BER, and control path testing which includes ARM based micros and GPIO/MDIO/I2C protocols.
- Root-cause complex silicon, link training, and firmware bugs using protocol analyzers and traffic generators.
Benefits
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- company paid holidays
- paid sick leave
- vacation time
- Paid Family Leave
- other leaves of absence
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What This Job Offers
Job Type
Full-time
Career Level
Senior
