Physical Design Timing Engineer

DensityAI•Mountain View, CA

19d•$220,000 - $350,000

About The Position

Own Full chip and Block timing methodologies and execution to-signoff of our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator program from first silicon through scale-out.

Requirements

Exceptional abilities across the full physical design flow (synthesis, place & route, CTS, signoff) with emphasis on timing flows and methodologies
10+ years of experience on very high performance designs at advanced technology nodes (7nm or better) and 2.5D/3D timing flows
Hands-on with industry-standard PD tools (Cadence Innovus, Synopsys Fusion Compiler, or equivalent) and signoff (PrimeTime, Tempus, or equivalent)
Demonstrated ability to work closely with architects, RTL designers, EDA vendors, and foundries to design and sign off complex chips
Post silicon characterization and process targeting experience is highly desirable

Nice To Haves

Multi-die packaging (CoWoS, 2.5D / 3D), thermal / IR / EM signoff, signal integrity, or DFT-aware physical design

Responsibilities

Own Full chip and Block timing methodologies and execution to-signoff of our AI accelerator silicon.
Use and develop AI-assisted tool flows to accelerate physical design timing convergence and signoff timelines.