Physical Design Timing Engineer (STA)

Broadcom•San Jose, CA

7d•$141,300 - $226,000

About The Position

The Full Chip Static Timing Analysis (STA) Engineer is responsible for ensuring that ASIC meets its performance targets and timing requirements across all operating conditions. This role involves owning the final timing closure for ASIC, performing quality checks across all process, voltage, and temperature (PVT) corners. The engineer will also be responsible for constraint development, including authoring, validating, and maintaining SDC for various modes. Analyzing foundry guidelines and incorporating sign-off corners, margins, and derates into timing analysis flows and methodologies are key aspects of this position. The role requires a deep understanding of advanced timing concepts such as On-Chip Variation (AOCV/POCV), Signal Integrity (crosstalk), and IR-drop aware STA. Managing and analyzing hundreds of timing scenarios for Multi-Mode Multi-Corner (MMMC) analysis is crucial for ensuring reliability across diverse operating environments. The engineer will also be involved in Timing ECOs, automating, generating, and implementing ECOs to fix setup, hold, and transition violations. High proficiency in scripting languages like Tcl, Python, and Perl is essential for automating analysis flows and data mining. This role requires cross-functional collaboration with RTL, Physical Design, and DFT teams to resolve complex timing issues and define guard-banding requirements. Analyzing and understanding the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows, and documenting best practices and lessons learned for continuous improvement are also key responsibilities.

Requirements

Bachelor’s degree in Electrical Engineering or Computer engineering
A minimum of 12 years of hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools
Experience in driving timing closure by effectively managing on-chip variation derates, optimizing multi-mode multi-corner constraints
Well versed with scripting languages like TCL and Python, PERL, or Shell
Strong problem solving skills with attention to every technical aspect
Be a strong team player with clear and precise communication skills
Expert proficiency in industry-standard sign-off tool

Responsibilities

Full-Chip Timing Sign-off: Own the final timing closure for ASIC, performing quality checks across all process, voltage, and temperature (PVT) corners
Constraint Development: Author, validate, and maintain SDC for various modes, including functional and test modes (Scan, MBIST,ATPG)
Analyze foundry guidelines and work with the team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologies
Deep knowledge of On-Chip Variation (AOCV/POCV), Signal Integrity (crosstalk), and IR-drop aware STA
Manage and analyze hundreds of timing scenarios to ensure reliability across diverse operating environments
Automate, generate and implement ECOs to fix setup, hold, and transition violations in the design cycle
High proficiency in Tcl (primary for EDA tools), Python, and Perl for automating analysis flows and data mining.
Partner with RTL, Physical Design, and DFT teams to resolve complex timing issues and define guard-banding requirements
Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows
Document best practices and lessons learned to drive continuous improvements in future projects