Physical Design Manager
About The Position
In this role, you will contribute to both the physical design and methodology development for future generations of high-performance processor and accelerator silicon, implemented in leading-edge CMOS process technologies. These designs are directly targeted at AI training and inference, cloud compute, and high-bandwidth networking applications, where power, performance, and scalability are critical. You will work at the intersection of advanced physical design, timing closure, and AI-driven compute demands, helping to enable custom silicon solutions that accelerate innovation across the data infrastructure ecosystem.
Requirements
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience or equivalent professional experience in lieu of a formal degree
- Principal-level physical design expertise with a proven track record delivering timing-closed ASICs or complex SoCs
- Demonstrated success in timing analysis and closure across multiple designs
- Deep understanding of advanced timing concepts including SI, CDC, LVF, POCV, and related methodologies
- Strong proficiency with PD and STA tools (e.g., Synopsys PrimeTime or equivalent), scripting, and UNIX/Linux environments
- Strong written and verbal communication skills with the ability to articulate technical tradeoffs
- Experience leading PD engineers in a first-line, hands-on capacity
- Proven ability to operate as a player-coach, contributing technically while guiding others
- Experience mentoring engineers and developing PD talent through active engagement
- Ability to coordinate execution across cross-functional teams with clear ownership and accountability
Nice To Haves
- Experience owning full-chip or large-subsystem PD and timing closure
- Familiarity with timing methodology and flow development
- Experience working with multi-site or globally distributed teams
- Experience balancing FTE and contractor resources
Responsibilities
- Serve as the primary technical owner for physical design and timing closure on assigned blocks, partitions, or subsystems
- Perform hands-on physical design and timing analysis, including late-stage debug and convergence
- Define and actively drive closure strategy, not just review results
- Act as a key technical escalation point, stepping in directly when progress stalls
- Lead and mentor a small team of PD engineers as a player-coach
- Provide prioritization, technical direction, and day-to-day execution guidance
- Coordinate closely with STA, RTL, CAD, and Program teams to resolve complex issues
- Support hiring, onboarding, and ramp-up of new team members while maintaining technical ownership
- Communicate execution status, risks, and tradeoffs clearly to engineering leadership
Benefits
- Relocation assistance will be provided for qualified candidates
- employee stock purchase plan with a 2-year look back
- family support programs to help balance work and home life
- robust mental health resources to prioritize emotional well-being
- recognition and service awards to celebrate contributions and milestones
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What This Job Offers
Job Type
Full-time
Career Level
Principal
