Physical Design Implementation and Signoff Methodology Lead & Architect

Altera•San Jose, CA

16d•$231,500 - $341,075•Onsite

About The Position

Altera is seeking a Physical Design Implementation & Signoff Methodology Lead & Architect to revolutionize the implementation and signoff methodology for all Altera tapeouts. This senior individual-contributor role requires an architect's mindset to build AI/ML-driven flows, standards, and quality gates that enhance speed, quality, and confidence across all future products. The role focuses on place-and-route implementation, electromigration and IR-drop (EMIR) analysis, timing signoff, and power signoff, with a focus on architecting scalable flows for concurrent designs. This position is part of Altera's senior IC technical ladder (Senior Principal Engineer / Principal Engineer), emphasizing leadership through expertise, architecture, and influence.

Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field, plus 15+ years (for Senior Principal Engineer) or 12+ years (Principal Engineer) of physical design experience, including a minimum of 8 years developing and deploying implementation or signoff methodology.
Deep, hands-on expertise in physical design implementation and signoff methodology, including electromigration and IR-drop (EMIR) analysis.
Strong command of timing signoff (STA) and power signoff flows, and the industry standards that govern them.
Deep, demonstrated expertise in at least two of the three core domains — place-and-route implementation, EMIR analysis, and timing/power signoff — with working command of the third. Depth across all three is preferred.
A demonstrated track record of architecting and deploying PD implementation and signoff methodologies across multiple tapeouts and process technology nodes.
Hands-on proficiency with industry-standard place-and-route, EMIR, STA, and power signoff tools (e.g., Ansys RedHawk-SC, Synopsys PrimeTime/PrimePower/Fusion Compiler, Cadence Innovus/Voltus/Tempus, or equivalent).
An AI/ML-driven mindset and working knowledge of applying AI/ML techniques (e.g., predictive modeling, ML-based EDA optimization, generative flow automation) to physical design implementation and signoff.
Excellent cross-functional collaboration and communication skills, with the ability to influence design methodology across multiple teams and sites.
Scripting and automation proficiency (Python, Tcl) sufficient to build methodology infrastructure and integrate ML pipelines directly.
A genuine can-do attitude — comfortable rolling up your sleeves and jumping into execution at any stage of the design cycle.

Nice To Haves

Direct experience deploying AI/ML-based EDA solutions in production flows (e.g., ML-driven timing/power/IR prediction, automated ECO generation, anomaly detection in signoff data).
Experience defining methodology strategy at a Principal or Senior Principal Engineer level across multiple product generations.
Experience working directly with foundry PDKs and technology qualification for leading-edge process nodes.
Patents, publications, or conference contributions in physical design implementation, signoff, or AI/ML-for-EDA domains.

Responsibilities

Own the end-to-end physical design implementation and signoff methodology strategy, including place-and-route implementation, electromigration and IR-drop (EMIR) analysis, timing signoff, and power signoff, across Altera's product portfolio.
Define and continuously improve PD implementation and signoff flows and standards, ensuring accuracy, full coverage, and efficient turnaround time for every design team.
Champion an AI/ML-driven mindset across implementation and signoff, introducing predictive and generative techniques for improved engineering productivity and quality.
Architect implementation and signoff flows to scale efficiently across a growing number of concurrent designs, enabling faster and more predictable closure.
Partner with process/technology teams, EDA vendors, and design teams to qualify and deploy next-generation implementation, EMIR, timing, and power methodologies for advanced process nodes.
Establish golden reference flows, signoff criteria, and quality gates that protect silicon reliability and drive first-pass tapeout success.
Lead root-cause analysis of complex implementation, EMIR, timing, and power signoff issues, and drive convergence across block-level and full-chip integration.
Serve as the go-to technical authority in tapeout readiness reviews, technology qualification forums, and cross-functional design reviews.
Evaluate, qualify, and help adopt emerging EDA tools, AI/ML-based flows, and methodologies.
Mentor design and CAD engineers on physical design implementation and signoff best practices.