Physical Design Engineering Graduate Intern

Intel•Folsom, CA

20h•Onsite

About The Position

Join Intel as a Physical Design Engineering Graduate Intern and contribute to shaping the future of silicon innovation. This hands-on role is an exciting opportunity to be part of the physical implementation of state-of-the-art silicon designs that power Intel's cutting-edge technologies. You will work with a multidisciplinary team to optimize designs for manufacturability and performance, while developing critical skills and exploring pathways for career growth. As an intern, you will make impactful contributions to Intel's business goals and gain invaluable experience in a highly collaborative and learning-oriented environment.

Requirements

Currently pursuing a master’s degree in electrical engineering or computer engineering, or a related technical specialized field.
3+ months of experience with the following skills: Proficiency in physical design tools and flows, including design planning tools, floor planning, and static timing analysis.
Knowledge of low-power design techniques and power reduction methodologies.
Familiarity with clock tree synthesis and design optimization principles.
Demonstrated ability to analyze and solve complex technical problems.

Nice To Haves

Strong communication and collaboration skills to work effectively in cross-functional teams.
Eagerness to explore and learn about design scalability, automation, and innovative approaches to physical design challenges.
Passion for continuous improvement and self-driven development in a dynamic environment.
Ability to adapt to new tools, techniques, and industry trends in silicon design.

Responsibilities

Support physical design implementation processes, including synthesis, place-and-route, timing analysis, clocking, and/or integration.
Assist in verification and signoff activities to ensure manufacturability and performance compliance of silicon designs.
Collaborate with cross-functional teams to enhance design scalability and automation efforts.
Apply design optimization techniques to improve power, performance, and area efficiency in silicon designs.
Perform floor planning and clock tree synthesis to achieve robust physical designs.
Contribute to static timing analysis to meet critical timing constraints for manufacturability.
Explore innovative solutions for low-power design and power reduction strategies in physical design workflows.
Embrace continuous learning and problem-solving to support Intel's commitment to advancing technology leadership.