Physical Design Engineer

Apple•Cupertino, CA

3d•Onsite

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA.

Requirements

Master’s degree or foreign equivalent in Electrical and Computer Engineering, or related field.
Utilizing PNR tools like ICC / ICC2 / Innovus to be used for place and route, including floor planning, placement, clock optimization, routing, timing and power optimization for the design of partitions on SoCs.
Utilizing timing analysis tools like Synopsys PrimeTime to be used for timing analysis, and timing ECO generation for timing closure of partitions on SoCs.
Utilizing TCL / Perl / Python and Unix scripting to summarize data, improve execution efficiency and implement custom scripts to aid partition closure.
Understanding of PD construction and analysis flow and methodologies to be able to successfully execute on, close and signoff partitions on SoCs.
Understanding transistors and digital circuits to meet specific requirements and make appropriate trade-offs during implementation, closure and signoff of partitions on SoCs.
Understanding results from EMIR analysis tools like Voltus or Redhawk and generating fixes to address violations or improve QoR.
Understanding results from Physical verification tools like calibre and generating fixes to address violations.

Responsibilities

Collaborate with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
Complete the net list to GDS2 implementation for partition(s), meeting schedule and design goals.
Perform timing, physical, and electrical verification, and driving signoff closure for the partitions.
Generate and implement ECOs to rectify timing, noise, and EM IR violations.
Resolve design and flow issues related to physical design, while identifying potential solutions and driving execution.
Drive optimization of PnR partitions to achieve the best Power/Performance/Area.
Streamline the timing signoff criteria, timing analysis methodologies, and flows (critical path spice simulation), and develop/enhance auto ECO generation scripts for timing closure.
Responsible for hands-on physical implementation and timing closure of core platforms and Socs.