Physical Design Engineer

Broadcom • San Jose, CA

2d

About The Position

The ASIC Products Division at Broadcom has developed some of the most complex IC solutions and technologies over the last two decades. Our products power the internet in areas such as machine learning, cloud computing, wireless infrastructure, and networking. We develop some of the most advanced technologies in the industry encompassing 3D and 2.5D interconnects. We are seeking a design engineer with physical layout skills to develop our next generation products with a focus on parallel interfaces. The job requires aspects of a successful layout engineer, an electrical background, a strong interest in 2.5D and 3D IC development, and new technology pathfinding. The candidate will work on a mix of customer products and development of new interconnect technologies and IP for MCM, 2.5D, and 3D ICs, working alongside R&D, IP development, customers, and manufacturing partners. This is an exciting opportunity to develop new ideas, design the next generation of leading edge ASIC products, and work on the most advanced technologies in the industry.

Requirements

• Independent, self-starter who can work across a worldwide organization and customer base.
• Ability to manage multiple concurrent customers under short timelines.
• Comfort with providing guidance and direction with incomplete information.
• Experience with various IC, Package and PCB layout databases and tools.
• Strong TCL, Python scripting experience to automate routine tasks.
• Bachelor's degree in Electrical Engineering or Computer Science and 12+ years related work experience; or a Master's degree in Electrical Engineering or Computer Science and 10+ years related work experience.

Responsibilities

• Design implementation and physical layout implementation of power grids, 2.5D and 3D die-die interconnects.
• DRC, LVS, and electrical checking.
• Ability to automate common processes and design steps.
• Development of high-speed signal interconnects working alongside SI and PI engineers.
• Electrical analysis and optimization of ubump and RDL patterns.
• Evaluation and development of new 2.5D and 3D interconnect technologies.
• Technology and testchip roadmapping with a focus on advanced packaging.

Benefits

• Discretionary annual bonus
• Competitive new hire equity grant
• Annual equity awards
• Medical plans
• Dental plans
• Vision plans
• 401(K) participation
• Company matching for 401(K)
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave
• Vacation time
• Paid Family Leave
• Other leaves of absence

What This Job Offers

• Job Type: Full-time
• Career Level: Senior