Senior/Principal Physical Design Engineer (remote)
About The Position
We are seeking an experienced Physical Design / P&R Engineer to take a key role in delivering complex, high-performance ASICs from RTL/netlist through GDSII and tapeout. The role owns critical aspects of physical implementation, including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and PPA optimization, using advanced technologies such as RISC-V, DDR, and SerDes. The engineer will use industry-leading tools, including Synopsys Fusion Compiler and Siemens Calibre, to solve physical design problems and help deliver successful silicon outcomes while collaborating with a multidisciplinary ASIC engineering team. The position includes full-chip implementation from synthesized netlist through GDSII, physical verification and signoff, static timing analysis, design optimization, and support for chip integration and tapeout. It also contributes to physical design flows, automation, design reviews, mentoring, and the team's internal capabilities.
Requirements
- 10+ years of direct industry experience with ASIC and/or SoC design.
- BSEE/MSEE or equivalent.
- Excellent problem-solving skills and attention to detail.
- Experience with industry-standard development tools and methodologies.
- Familiarity with RISC architectures such as ARM or MIPS.
- Proficiency in Synopsys Design Compiler and other EDA tools.
- Proven track record of first-pass successes.
- Ability to work independently as a self-starter and assume leadership roles.
- Strong background in RTL-based digital IC design using Verilog/SystemVerilog.
- Strong understanding of digital design principles.
- Willingness to mentor and develop less experienced engineers.
Responsibilities
- Analyze and optimize designs to meet power, performance, and area (PPA) objectives while satisfying timing, signal integrity, reliability, and manufacturability requirements.
- Collaborate with RTL design, verification, DFT, analog/mixed-signal, packaging, and other engineering teams to support chip integration.
- Develop and optimize floorplans incorporating complex IP and high-speed interfaces, including DDR and SerDes.
- Develop, maintain, and improve physical design flows, scripts, methodologies, and automation.
- Identify and resolve congestion, routing, timing, power integrity, and physical verification issues.
- Participate in design reviews and recommend floorplanning, physical architecture, implementation strategies, and PPA tradeoffs.
- Implement full-chip physical design from synthesized netlist through GDSII, including floorplanning, power planning, placement, CTS, routing, optimization, and timing closure.
- Perform physical verification and signoff using Siemens Calibre, including DRC and LVS verification and resolution of physical design violations.
- Perform static timing analysis and drive timing closure across operating modes, process corners, and design constraints.
- Provide technical guidance and mentoring to other engineers and contribute to the development of internal physical design capabilities.
- Support final design signoff and tapeout, ensuring physical design and verification requirements are satisfied.
- Support integration and physical implementation of third-party and internally developed IP blocks.
- Support physical implementation and integration of RISC-V processor-based designs and subsystems, including timing, power, and physical design considerations.
- Troubleshoot complex implementation and signoff issues and drive corrective actions through resolution.
- Use Synopsys Fusion Compiler for physical implementation, optimization, and design closure.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
