Physical Design Engineer

Apple • Cupertino, CA

3d • Onsite

About The Position

Analyze and perform static and dynamic power reduction of the advanced node technology and complex SoC design. Implement the low power design techniques and meet the power target goals. Perform critical ECOs (Engineering Change Orders) to fix the identified violations from the analysis of all design aspects, such as Timing, Physical verification, Power Grid integrity, and Logic equivalent checks for design closure for tape out. Perform scripting and programming for CAD tool flow development for automation problem solving and efficiency improvement. Execute chip/partition floor planning, pin assignment, macro placement, and evaluation of logic placement to improve design power, performance and area. Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. Timing, physical and electrical verification and driving the signoff closure for the partitions. Resolve and improving design and flow issues related to physical design, identify potential solutions, and drive execution.

Requirements

• Master's degree or foreign equivalent in Computer Engineering or related field and 3 years of experience in the job offered or related occupation.
• Utilize Innovus or Fusion Compiler APR tools to perform implementation design, including applying these tools in physical design workflows and supporting execution of implementation design tasks.
• Tune implementation design flows and methodologies to improve the power, performance, and area of designs.
• Perform static timing analysis and apply timing convergence techniques, conduct IR/IVD analysis, implement violation fixes, and debug and resolve LVC/DRC violations.
• Perform physical design on advanced technology nodes (7nm and below), with knowledge of modern CMOS technology and fabrication fundamentals.
• Perform block level physical design, including floor planning, placement, clock tree synthesis, routing, and ECO step implementation.
• Utilize lower power design techniques, including clock gating, power gating, and multi-voltage domain design.
• Utilize scripting language, TCL, Perl, or Python to implement automatic techniques.
• Apply top down and bottom up design approaches and resolve interblock design issues related to timing and PDV related issues.

Responsibilities

• Analyze and perform static and dynamic power reduction of advanced node technology and complex SoC design.
• Implement low power design techniques and meet power target goals.
• Perform critical ECOs to fix identified violations.
• Perform scripting and programming for CAD tool flow development.
• Execute chip/partition floor planning, pin assignment, macro placement, and evaluation of logic placement.
• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
• Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
• Perform timing, physical, and electrical verification and drive signoff closure for partitions.
• Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior