Physical Design Engineer

Altera•San Jose, CA

5d•$105,000 - $120,000•Onsite

About The Position

Altera is looking for a Physical Design Engineer to join our Silicon Engineering organization. In this role, you will contribute to the physical implementation of next-generation FPGA products, partnering closely with architecture, RTL design, DFT, timing, power, and verification teams to help deliver high-quality silicon. This is an excellent opportunity for an early-career engineer or recent graduate with a Master’s degree who is looking to grow technical depth in physical design and backend implementation in a fast-paced semiconductor environment. As a Physical Design Engineer, you will support block-level and/or top-level physical design implementation activities across FPGA product development. You will work closely with cross-functional teams to help optimize designs for timing, power, area, and manufacturability while contributing to the successful delivery of high-quality silicon.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related engineering field with 2+ years of industry experience in physical design, ASIC/SoC backend implementation, or a related semiconductor engineering role, including experience in the following:
Physical design fundamentals including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.
Experience with industry-standard physical design and signoff tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, Fusion Compiler, or similar tools.
Understanding of static timing analysis (STA), timing constraints, setup/hold concepts, and timing closure methodologies.
Experience reviewing and debugging timing, congestion, area, and power reports.
Familiarity with physical verification concepts including DRC/LVS and signoff quality checks.
Exposure to scripting or automation using Tcl, Python, Perl, or similar languages.
Knowledge of semiconductor design flows, from RTL handoff through physical implementation and signoff.
Strong understanding of digital design fundamentals and CMOS/VLSI concepts.
Applicants must be eligible for any required U.S. export authorizations.

Nice To Haves

Master’s degree in Electrical Engineering, Computer Engineering, or related field.
Experience with advanced-node physical design methodologies and low-power implementation concepts.
Exposure to FPGA, SoC, or high-performance semiconductor product development.
Familiarity with power planning, IR drop analysis, signal integrity, electromigration (EM) analysis, or physical signoff flows.
Experience working in Linux/Unix-based development environments.
Strong problem-solving skills and the ability to work effectively in a collaborative team environment.

Responsibilities

Support block-level and/or top-level physical design implementation for FPGA and ASIC-style designs, including floorplanning, placement, clock tree synthesis, routing, and physical verification.
Work with senior physical design engineers to optimize designs for timing, power, area, congestion, and routability.
Participate in implementation tasks across the physical design flow, including netlist handoff, constraints setup, synthesis/physical design handoff, and signoff readiness.
Run and analyze timing, power, congestion, and design rule reports to identify issues and support closure activities.
Collaborate with RTL, design, DFT, CAD, and verification teams to resolve design and flow issues impacting physical implementation.
Support static timing analysis (STA), timing closure, and engineering change order (ECO) implementation activities.
Help debug physical design issues related to setup/hold violations, clocking, congestion, IR drop, or design rule violations.
Assist with physical verification tasks including DRC/LVS checks and design signoff preparation.
Develop and maintain scripts and automation to improve physical design productivity and flow efficiency.
Participate in silicon bring-up support and post-silicon debug activities as needed in partnership with cross-functional teams.