About The Position

NVIDIA is looking for best-in-class Physical Design Engineers with expertise in Synthesis to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in meaningful, growing and professional environment where you make a significant impact in a technology-focused company.

Requirements

  • BSEE, MSEE, or equivalent experience.
  • 2+ years of experience in synthesis and physical implementation on advanced process nodes.
  • Strong proficiency with Synopsys Fusion Compiler, Cadence Genus, or comparable synthesis tools.
  • Hands-on experience with synthesis constraints, timing analysis, QoR optimization, and the full place-and-route flow.
  • Strong analytical and debugging skills across RTL, synthesis, timing, and physical implementation.
  • Proficiency in Python, Perl, Tcl, and Make.
  • Strong communication and multi-functional collaboration skills.

Responsibilities

  • Own RTL-to-gate synthesis and QoR convergence for complex digital blocks and hierarchical partitions.
  • Optimize synthesis strategies, constraints, and flows to meet performance, power, and area targets.
  • Analyze design bottlenecks and QoR regressions, collaborating with RTL, timing, architecture, and physical design teams to resolve them.
  • Support physical implementation from floorplanning and power planning through routing and timing closure.
  • Automate design setup, execution, reporting, and issue triage while improving project-wide methodologies and best known methods.

Benefits

  • equity
  • benefits
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