Physical Design Engineer Intern, BS - Summer 2027

Marvell Technology•Austin, CA

2d•$29 - $57

About The Position

Marvell's Physical Design teams span across multiple domains, giving you the opportunity to work on technologies that power next-generation cloud, AI, storage, and networking solutions. Some teams focus their design work on supporting architecture to GDSII (Graphic Data System) implementation of ASIC and processor designs. Other teams focus on timing analysis for future designs of our next-gen high-performance data center chips in a leading-edge CMOS process technology. Across all groups, you’ll collaborate with your direct team and cross-functional partners, working through technical design challenges to ensure we meet the performance, power, and area requirements of an active design.

Requirements

Currently enrolled in a Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field with an expected graduation date between Fall 2027 – Summer 2028
Completed courses focusing on VLSI, digital logic, circuit design, computer architecture, RTL synthesis, Verilog or SystemVerilog, place and route, static timing analysis, digital systems, or microelectronics
Proficiency in programming & scripting languages like Python, TCL, Perl, and Shell
Experience working in a Unix type environment
Experience using tools like Synopsys (PrimeTime), Cadence (Tempus), and Mentor
Strong analysis, problem solving, and communication skills

Responsibilities

Perform synthesis, floor planning, place and route, clock insertion, timing analysis, and timing closure on complex logic blocks using industry standard EDA tools (PrimeTime, Tempus)
Write scripts in Python, TCL, Perl, and Shell to aid design and development activities
Utilize problem solving skills to analyze, debug, and implement fixes for design violations using CAD tools
Collaborate with RTL, Synthesis, and other Design teams to resolve congestion & timing bottlenecks, and ensure that all designs converge & integrate in a timely manner