About The Position

The Physical Design team within Cisco Silicon One owns backend methodology and flow development from RTL to GDS. The team plays a critical role in developing high-quality VLSI designs for some of Cisco's most advanced silicon products. We work with the latest silicon technologies and processes to build large-scale, complex devices that push the boundaries of feasibility. You will collaborate with experienced engineers across architecture, design, verification, and implementation to deliver high-performance silicon. You will join a dynamic engineering team focused on defining, designing, and verifying ASIC and ASIC subsystems for Cisco’s diverse range of platforms. Our team contributes to the full product lifecycle, ensuring we meet power, performance, and area goals for our products. We focus on designing, documenting, and developing high-quality ASIC subsystems for high-volume deployment. Additionally, we actively define the processes, methods, and tools necessary for the implementation of complex, next-generation developments. You will be part of the Cisco Silicon One team, which is at the heart of Cisco's software and ASIC design efforts. As a Physical Design Engineer, you will contribute to backend implementation work across key stages of chip design, helping move complex designs from RTL toward GDS. You will work on physical synthesis, place and route, optimization, timing closure, and floor planning activities. Success in this role means delivering high-quality implementation results, learning quickly from senior engineers, and helping improve the flow and methodology used by the team.

Requirements

  • B.Sc or M.Sc Electrical Engineering or Computer Engineering graduate (or any other relevant fields)
  • Right to work in Spain.
  • Fluent in English and Spanish.

Nice To Haves

  • Up to 2 years of relevant experience is a plus.
  • Scripting skills and coding are a nice to have.

Responsibilities

  • Defining, designing, and verifying ASIC and ASIC subsystems for Cisco’s diverse range of platforms.
  • Contributing to the full product lifecycle, ensuring power, performance, and area goals are met.
  • Designing, documenting, and developing high-quality ASIC subsystems for high-volume deployment.
  • Defining the processes, methods, and tools necessary for the implementation of complex, next-generation developments.
  • Contributing to backend implementation work across key stages of chip design, moving complex designs from RTL toward GDS.
  • Working on physical synthesis, place and route, optimization, timing closure, and floor planning activities.
  • Delivering high-quality implementation results.
  • Learning quickly from senior engineers.
  • Helping improve the flow and methodology used by the team.
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