Physical Design Engineer, AI Accelerator IP

Tenstorrent•Toronto, ON

3h•$100,000 - $500,000•Hybrid

About The Position

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent licenses RISC-V and AI IP to customers who need hardened, PPA-proven deliverables on their target node and foundry. This role owns physical implementation of those IP blocks end to end, from synthesis through PnR, timing closure, and GDSII signoff, and directly determines how fast we can commit to a customer's timeline. This role is hybrid, based out of Toronto, ON; Austin, TX; or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Requirements

BS/MS/PhD in EE/ECE/CE/CS with 5+ years of block-level or IP-centric physical design through tapeout.
Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl).
Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC).
Experience building floorplans, power grids, pin placement, and clocking strategies.
Experience delivering IP integration collateral (LEF/DEF, timing and power models, GDS, signoff reports).

Nice To Haves

A hands-on physical design engineer who owns blocks end to end, with a track record of block-level and IP tapeouts on advanced nodes.
Driven by PPA outcomes, working closely with RTL owners to close critical paths and hit power budgets.
Rigorous about signoff quality, because our IP ships to customers who integrate it without you in the room.

Responsibilities

Owns physical implementation of IP blocks end to end, from synthesis through PnR, timing closure, and GDSII signoff.
Drives PPA outcomes, working closely with RTL owners to close critical paths and hit power budgets.
Ensures signoff quality for IP that ships to customers.
Builds floorplans, power grids, pin placement, and clocking strategies.
Delivers IP integration collateral (LEF/DEF, timing and power models, GDS, signoff reports).