Physical Analysis Engineer

Apple•Cupertino, CA

2d•$150,400 - $225,300•Onsite

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Debug flow related issues and make enhancements as appropriate. Work with all aspects of ASIC physical design including floor planning, clock and power distribution. Use industry standard tools to perform analyses such as Apache Redhawk, Voltagestorm, ETS, PT-SI. Perform various electrical analyses at the chip level, including but not limited to Static/Dynamic IR, EM, Noise and Signal EM. Work multi-functionally with the CAD/technology teams for flow bring up and validation. Collaborate with the implementation team during the entire chip design cycle to drive signoff closure for tape out. Manage schedules and supporting multi-functional engineering effort. 40 hours/week.

Requirements

Bachelor’s degree or foreign equivalent in Electrical Engineering, Mechatronic Engineering, or related field.
Designing, simulating, and validating large SOC PDN (power grid network) with complex structure in the advance technology process node.
Performing static and power analysis to signoff on the power grid using tools like Ansys RedHawk, or Cadence Voltus.
Utilizing problem-solving skills, with the ability to debug complex EMIR violations and propose appropriate and effective design fixes.
Conducting static and dynamic power analysis, analyzing and verifying low power techniques such as power gating, clock gating, to meet project power/IR budgets.
Performing chip-package co-analysis to identify PDN weakness, such as that caused by dynamic voltage droop, high impedance paths or insufficient decoupling, and assess impact on critical timing paths.
Creating or automating complex, multi-step engineering workflows, leading to significant reduction in manual efforts and cycle time, using conventional scripting language such as Perl, Tcl, or Python.
Utilizing post-silicon correlation, collecting and processing DFT scan patterns out of characterization results, and refining pre-silicon EMIR models and signoff methodologies for future projects.

Responsibilities

Debug flow related issues and make enhancements as appropriate.
Work with all aspects of ASIC physical design including floor planning, clock and power distribution.
Use industry standard tools to perform analyses such as Apache Redhawk, Voltagestorm, ETS, PT-SI.
Perform various electrical analyses at the chip level, including but not limited to Static/Dynamic IR, EM, Noise and Signal EM.
Work multi-functionally with the CAD/technology teams for flow bring up and validation.
Collaborate with the implementation team during the entire chip design cycle to drive signoff closure for tape out.
Manage schedules and supporting multi-functional engineering effort.