Photonic Engineer, Senior

Qualcomm•Santa Clara, CA

4d•$147,900 - $221,900

About The Position

Define, design, and develop photonic integrated circuits for next-generation silicon photonics platforms used in high-speed optical interconnect and DWDM transceiver applications. Design active and passive photonic components using 3D structure simulation tools and foundry PDKs, and collaborate with designers and systems teams on a DWDM transceiver product project. Use script-based workflows, including AI-assisted tooling, to automate simulation, layout generation, and data analysis. Work with testing engineers on post-fabrication characterization to validate designs and connect simulation results with hardware measurements. The role works under some supervision while allowing high independence in component-level design decisions. It provides technical guidance and layout-review feedback to layout engineers and junior team members, owns design deliverables, and communicates technical status and findings to EIC designers, packaging engineers, and systems architects. The engineer completes tasks spanning simulation, layout, and characterization, works within tape-out schedules, reticle-area budgets, and PDK constraints, and contributes to component architecture and platform discussions.

Requirements

Bachelor's degree in EE, Physics, Optics, or a related field and 5+ years of PIC design experience; or a Master's degree in one of these fields and 3+ years of PIC design experience; or a PhD in one of these fields and 1+ year of PIC design experience.
At least 2 years of hands-on experience with Lumerical (FDTD, MODE, CHARGE, INTERCONNECT), a layout editor/viewer such as Cadence Virtuoso or KLayout, and Python.
Hands-on design experience with silicon-photonics foundry PDKs.
System-level understanding of optical link budgets, DWDM channel plans, OMA/TDECQ, and transceiver power allocation.
EDA tools: Lumerical (FDTD, MODE, INTERCONNECT), a layout editor/viewer such as Cadence Virtuoso or KLayout, and Python or equivalent.
The posting also lists minimum qualifications of a Bachelor's degree in Electrical Engineering with 3+ years of RF/analog circuit design experience for wireless products and 2+ years of ASIC design, verification, or related experience; or a Master's degree in Electrical Engineering or a related field with 2+ years of ASIC design, verification, or related experience; or a PhD in Electrical Engineering or a related field.
At least 2 years of academic or professional experience using two or more of CADENCE, Virtuoso, and ADS.

Nice To Haves

At least 2 years of Co-Packaged Optics (CPO) design experience, such as chip-to-chip optical coupling, CPO-specific constraints, or tape-out in a CPO-targeted node.
At least 2 years of PIC-EIC co-design experience, including joint optimization for high-speed transceivers and driver/TIA co-simulation with active photonic devices.
Experience with system-level photonic simulation tools such as VPI Photonics, Lumerical Zemax OpticStudio, or equivalent.
Experience with DWDM wavelength control loops, thermal tuning, and closed-loop resonance lock for ring-modulator transmitters.
Track record of photonic tape-outs (MPW or full-reticle) with post-silicon characterization closure.
Publication record or patent filings in integrated photonics.
Experience with MATLAB, VPI Photonics, or Lumerical Zemax OpticStudio.

Responsibilities

Design active photonic devices, including MRM, MZM, and photodetectors, and passive devices, including edge and grating couplers, power splitters, and wavelength MUX/DEMUX, from specification through tape-out using foundry PDKs and 3D optical simulation.
Perform 3D photonic simulation using FDTD, MODE, INTERCONNECT, and CHARGE for carrier and electro-optic effects; validate device performance and iterate toward target specifications.
Develop and maintain script-based workflows, leveraging AI-assisted tooling, to automate parameter sweeps, layout generation, and measurement-data processing.
Review and sign off on PIC physical layouts produced by the dedicated layout engineer.
Collaborate with PIC designers, EIC designers, and package teams on co-simulations; align interface specifications and validate electro-optical performance in the full DWDM transceiver system.
Execute and interpret post-fabrication characterization lab testing.
Correlate characterization data with models, close the simulation-to-hardware loop, and propose corrections.
Participate in cross-functional design reviews covering component performance, tape-out readiness, and system link budget.
Maintain internal technical documentation, including design specifications, simulation methodology, characterization reports, and tape-out checklists.
Track developments in silicon photonics, CPO, and DWDM transceivers and apply emerging techniques to improve design quality and time-to-tape-out.
Provide technical guidance and layout-review feedback to layout engineers and junior team members.
Communicate technical status, simulation results, and characterization findings to EIC designers, packaging engineers, and systems architects.
Prioritize parallel workstreams and exercise engineering judgment to diagnose simulation-versus-measurement discrepancies when data is incomplete or conflicting.