Ph.D. Intern - Analog, Mixed Signal & Circuit Design

Marvell Technology • Irvine, CA

4d • $38 - $76

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Every time a hyperscaler trains a frontier AI model, streams a zettabyte of data across a data center fabric, or pushes a coherent optical signal across a transoceanic link, analog and mixed-signal circuits are doing the work that makes it possible. At Marvell, our analog design team is the reason those circuits exist. The custom XPUs, the 224G and 448G SerDes IP, the Silicon Photonics light engines, the co-packaged optics platforms powering the world's largest AI infrastructure — none of it ships without the analog IP this team designs from scratch. This is one of the few places in the industry where analog engineers work at the true physical limit of what silicon can do, on problems at and beyond 448G that have no established design playbook and no known solutions — open research questions that require exactly the kind of rigorous, first-principles thinking a Ph.D. program is built to develop. Our Ph.D. Intern Program embeds doctoral candidates directly inside active design teams, working alongside staff and distinguished engineers on production IP and research-stage silicon. Projects are selected because they sit at the intersection of Marvell's most pressing engineering challenges and the circuit theory, device physics, and signal processing that define doctoral research in electrical engineering. Interns work through the complete design flow and participate in a structured analog design curriculum alongside their peers. What you will take away from this program is something no coursework can replicate: the experience of seeing your own research become real, working silicon, deployed at scale inside the world's most advanced AI infrastructure.

Requirements

• Experience designing analog and mixed-signal circuits at the transistor level.
• Currently enrolled in a Ph.D. program in Electrical Engineering or a related field, with a research focus in analog, mixed-signal, or RF circuit design
• Demonstrate hands-on experience designing and simulating analog circuit blocks such as PLLs, SerDes building blocks, ADCs, DACs, LDOs, amplifiers, or high-speed I/O — not just theoretical familiarity
• Apply strong fundamentals in transistor-level circuit design, including device physics, noise analysis, stability, and low-power techniques in advanced CMOS processes
• Simulate and verify designs independently using industry-standard tools such as Cadence Virtuoso and Spectre; experience with MATLAB or Python for system-level modeling is a plus
• Communicate design decisions and tradeoffs clearly — you will be expected to present your work to the engineering team and defend your approach

Nice To Haves

• Experience designing in FinFET process nodes (7nm, 5nm, 3nm, or equivalent)
• Familiarity with high-speed serial link architectures, optical transceiver circuits, or Die-to-Die interconnect design
• Exposure to layout-aware design, parasitic extraction, or post-layout simulation
• Experience with behavioral modeling in Verilog-A or similar

Responsibilities

• Design, simulate, and verify analog and mixed-signal circuit blocks across the full design flow — from architecture and schematic through simulation, layout coordination, and silicon bring-up
• Work on production-grade IP including high-speed SerDes building blocks, Silicon Photonics driver and receiver circuits, ADC/DAC architectures, PLLs, clock distribution networks, LDOs, and other precision analog circuits in advanced CMOS FinFET processes
• Use industry-standard tools including Cadence and MATLAB throughout your project
• Collaborate directly with layout engineers to implement your designs and iterate based on simulation and silicon feedback
• Attend and contribute to design reviews alongside the full engineering team
• Present your work — both the research framing and the design results — to the engineers around you
• Participate in a structured analog design curriculum alongside your Ph.D. intern peers

Benefits

• medical, dental, and vision coverage
• perks and discounts
• robust mental health resources to prioritize emotional well-being
• paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Intern
• Education Level: Ph.D. or professional degree