Ph.D. Intern - AI/ML & Design Automation

Marvell Technology•Irvine, CA

1d•$37 - $73

About The Position

Marvell is building the silicon that makes AI possible, and designing this silicon at the pace and complexity the AI era demands requires intelligence applied to the design process itself. Marvell's AI and machine learning teams are working on using AI to accelerate how silicon is designed, verified, and deployed, and building the enterprise AI infrastructure that makes Marvell's engineering organization faster and smarter at every level. This Ph.D. intern pool spans two distinct but connected tracks: hardware-focused (applying ML and AI techniques directly to chip design challenges) and enterprise-focused (building and deploying internal AI tools and platforms). Both tracks sit at the frontier of applied AI research in a production semiconductor environment. Marvell's Ph.D. Intern Program places doctoral candidates directly inside these active efforts, working on problems that are inseparable from their academic research. The work done here is the applied dimension of doctoral research in machine learning, computer science, and electrical engineering, conducted at production scale, on real design data, with real consequences for the silicon that ships to the world's largest AI infrastructure operators. The experience gained is unique, offering the chance to deploy research inside one of the most complex engineering environments in the semiconductor industry.

Requirements

Currently enrolled in a Ph.D. program in Computer Science, Electrical Engineering, Data Science, or a related field, with a research focus in machine learning, AI systems, or a related area.
Demonstrate applied experience training, evaluating, and deploying ML models using frameworks such as PyTorch or TensorFlow.
Write production-quality Python; familiarity with version control (Git) and software development best practices is required.
Apply rigorous experimental methodology — you design experiments, measure results, and draw defensible conclusions from data.
Communicate technical work clearly to both research and engineering audiences — you will present your work and defend your approach to the teams you work with.

Nice To Haves

Coursework or research experience in VLSI design, digital or analog circuit design, computer architecture, or EDA — sufficient to understand the design problems your models are solving.
Familiarity with graph-based ML methods (GNNs), reinforcement learning, or generative models applied to structured engineering data.
Exposure to EDA tools or chip design flows (Cadence, Synopsys, or equivalent) is a strong plus.
Design and implement agentic GenAI systems with demonstrated experience across the full stack — LLMs, multimodal models, RAG pipelines, and agentic protocols such as MCP and A2A.
Apply hands-on knowledge of SOTA architectures and frameworks including transformers, diffusion models, and orchestration tools such as LangChain, LangGraph, AutoGen, CrewAI, LlamaIndex, or Hugging Face.
Benchmark and evaluate model performance rigorously — you identify failure modes, propose enhancements, and back conclusions with data.
Experience with agentic reasoning, planning, and tool-use patterns in multi-agent orchestration frameworks such as n8n or AutoGen.
Exposure to end-to-end data pipeline development and model deployment in collaboration with data engineering or platform teams.
Demonstrated ability to independently research and implement concepts from current AI literature and apply them in a working system.

Responsibilities

Develop and apply ML models — including graph neural networks, reinforcement learning, and generative approaches — to chip design tasks such as placement, routing, timing closure, power estimation, and design rule checking.
Work directly with production EDA tool flows and real design data from active tapeouts in 3nm and 2nm FinFET and Gate-All-Around processes.
Build predictive models that reduce design iteration cycles and improve first-pass silicon success rates.
Collaborate with analog, digital, and physical design engineers to identify high-value automation targets and validate model outputs against ground-truth silicon results.
Present research findings and model performance to engineering leadership and contribute to internal technical documentation.
Design, implement, and evaluate LLM-based tools and agentic workflows — including systems built on models such as Claude — for use by Marvell's global engineering and operations teams.
Build retrieval-augmented generation (RAG) pipelines, fine-tuning workflows, and prompt engineering frameworks grounded in Marvell's internal knowledge and tooling ecosystem.
Evaluate model performance, safety, and reliability in production enterprise environments and iterate based on real user feedback from engineering teams.
Collaborate with IT, security, and engineering stakeholders to ensure responsible and scalable AI deployment across the organization.
Present implementation results and adoption metrics to cross-functional leadership.