About The Position

Join Apple's SOC performance team within the Hardware Technologies organization to shape the architecture of future Apple devices. This role involves initiating and fostering deep collaboration between SOC architecture, design, power, and software teams to deliver world-class caches/memory systems. The ultimate goal is to provide the best customer experience by enabling seamless integration of CPUs, GPUs, Machine Learning, Camera, Display, and Connectivity components on our chips. We are looking for an upbeat and highly motivated SOC Performance Modeling SW Engineer to work on performance models and infrastructure.

Requirements

  • Bachelor's degree
  • Experience in hardware architecture and design issues
  • Experience coding in C++ and Python
  • Experience with computer architecture and software engineering principles
  • Experience with data structures and algorithms

Nice To Haves

  • MS or PhD in CS, EE or related field
  • 10+ years of relevant experience
  • Experience with multi-paradigm software development in C++
  • Experience with multi-language programming environments, and selecting the right tool or language for the job
  • Experience with compiler explorer and understanding the transformations the compiler is performing on your code
  • Experience thinking about code as something that will be read by both humans and machines, and instituting conventions, structure, and documentation that make a codebase tractable for AI-assisted reasoning and navigation
  • Experience with architectural, micro-architectural performance modeling

Responsibilities

  • Ensure Apple's ability to produce high quality, timely data to drive world-class hardware designs.
  • Collaborate with engineers across the organization to translate design space studies into well-written software models.
  • Transform the hardware execution model into high-performance C++.
  • Be involved with the full life-cycle of performance modeling, from early architectural exploration to post-silicon correlation.
  • Pay close attention to the performance, maintainability, and flexibility of the simulator, ensuring hardware architects can quickly iterate on experiments.
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