PCIe Hardware Engineer, Systems

Everpure•Santa Clara, CA

9h•Onsite

About The Position

We are seeking a highly motivated PCIe Hardware System Engineer, New Grad, for Pure’s Datastore team. Pure builds the industry’s most innovative, high-performance, energy-efficient and TCO-optimized storage solution. As part of this team, you will help validate and productize this differentiated storage solution for our customers. You will work with senior engineers across hardware, firmware, validation, and system teams to debug PCIe and NVMe issues, improve test coverage, and build automation that improves engineering efficiency.

Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Internship, academic project, research, or lab experience in one or more of the following areas: PCIe, NVMe, storage systems, embedded systems, server platforms, high-speed interfaces
Fundamental understanding of PCIe architecture and protocol concepts.
Familiarity with Linux environments and basic debug workflows.
Proficiency in Python, Bash, or similar scripting languages for automation or data analysis.
Basic understanding of C/C++ to read firmware source code and follow debug flows across hardware and firmware boundaries.
Strong problem-solving skills and willingness to work through complex issues methodically.
Good written and verbal communication skills.
Detail-oriented, analytical, and eager to learn in a fast-paced engineering environment.

Nice To Haves

Coursework or project experience with PCIe LTSSM, link training, protocol analyzers, or signal integrity concepts.
Exposure to NVMe architecture, SSD behavior, or storage protocol testing.
Familiarity with lab tools such as protocol analyzers, oscilloscopes, logic analyzers, or serial/UART tools.
Experience building test scripts, parsers, dashboards, or lightweight automation tools.
Exposure to ARM, x86, BIOS, firmware, or low-level system bring-up.
Basic understanding of AI tools such as Codex, Claude Code, or similar assistants, and basic understanding of RAG, agents, skills, and harness engineering. At Pure, we use AI in our daily work, so candidates should be comfortable learning and applying AI tools to improve debug, triage, automation, and validation efficiency.

Responsibilities

Support PCIe, NVMe, and SMBus issue triage raised during bring-up, validation, and regression testing.
Reproduce failures in the lab and collect key debug data such as logs, analyzer traces, and platform state.
Assist with PCIe Gen5 and Gen6 interface validation under the guidance of senior engineers.
Help develop and execute validation test plans for early chip bring-up and throughout the product development cycle.
Write Python, Bash, or similar scripts to automate test execution, log collection, and result analysis.
Analyze PCIe logs and traces to help identify failure patterns such as link training issues, degraded link speed, width reduction, and correctable errors.
Work closely with hardware and firmware engineers to narrow down issues at the system, protocol, or implementation level.
Document test results, debug findings, and open issues clearly and consistently.
Contribute to better validation workflows by leveraging automation and AI-based tooling where appropriate.
Learn how to use lab equipment such as PCIe analyzers, exercisers, oscilloscopes, I2C analyzers, and UART tools for structured debug.