PCIe Hardware Engineer, Systems

Pure Storage•Santa Clara, CA

19h•Onsite

About The Position

We are seeking a highly motivated Hardware PCIe Engineer for Pure’s Datastore team. Pure builds the industry’s most innovative, high-performance, energy-efficient and TCO-optimised storage solution. As part of this team, you will help productize this differentiated storage solution for our customers.

Requirements

Over 5 years of experience in advanced interface issue troubleshooting, root cause analysis, and solution identification, encompassing complex system-level interactions across host, PCIe, and CXL interfaces in enterprise server and SSD environments.
Developed and automated comprehensive validation and testing solutions.
BS in Electrical or Computer Engineering (or related field).
Proven track record in chip bring-up and product qualification.
Hands-on experience with PCIe Gen5/Gen6.
Proficient with test equipment including PCIe analyzer, Exerciser or Jammer, I2C analyzer, and UART.
Experience with PCIe compliance testing (SIG) for SSD products.
Proficient in scripting with Python, BASH, and similar languages.
Hands-on experience in a Linux environment.
Detail-oriented, analytical, process-driven, and customer-focused.
Thrive in fast-paced, evolving business environments.
Clear and effective communicator, both verbally and in writing.

Responsibilities

Own and drive the triage, root cause, and resolution of issues raised by internal teams, manufacturing, and JDMs.
PCIe Gen5 and Gen6 interfaces NVMe features SMBus
Ensure proper documentation and regular update to stakeholders throughout the triage to resolution journey.
Guide the development of PCIe, NVMe, and SMBus validation test plan for early phase chip bring-up and regression testing throughout the development cycle.
Lead failure analysis and root cause investigations to support field issues and customer escalations.
Leverage automation and AI to improve issue triaging, utilizing company-supported tools like Augment and Glean to facilitate agent development and harness advanced AI skills.
Provide technical leadership and mentorship to junior engineers.