Packaging Engineer- Flip Chip

Volantis Semiconductor, Inc. • Boston, MA

106d

About The Position

We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip). This spans bump metallurgy, substrate integration, reflow and underfill processes, reliability, failure analysis, and cross-functional support through package and system productization.

Requirements

• Strong experience in flip chip packaging and assembly processes for semiconductor devices.
• Deep understanding of bumping technologies (solder bumps, Cu pillar, micro-bumps) and UBM/metallization systems.
• Experience with underfill materials, dispense techniques, flow behavior, and cure processes.
• Understanding of thermo-mechanical behavior in flip chip assemblies (CTE mismatch, warpage, solder fatigue, reliability risks).
• Hands-on experience with failure analysis and reliability testing (cross-sections, SEM, CSAM, thermal cycling).
• Ability to work with OSATs and suppliers to develop and transfer assembly processes into production.
• Strong problem-solving skills with ability to debug yield and reliability issues in manufacturing environments.

Nice To Haves

• Experience with III-V packaging, photonics packaging, and precision chip attach.
• Experience with advanced packaging technologies including 2.5D interposers, 3D stacking, chiplets, and CoWoS-like architectures.
• Familiarity with bill of materials used in photonics packaging such as clear adhesives and underfills as well as mold compounds and underfills for 2.5D advanced packaging.
• Familiarity with fine-pitch micro-bump and hybrid bonding approaches.
• Experience integrating high-power or high-TDP devices with tight warpage and thermal constraints.
• Exposure to thermo-mechanical modeling or collaboration with simulation teams for warpage and reliability prediction.
• Understanding of system-level interactions (PCB attach, second-level interconnect reliability).

Responsibilities

• Develop and optimize flip chip attach processes including bump formation, placement, reflow, and underfill for high-performance semiconductor packages.
• Define and manage bump metallurgy stacks (e.g., Cu pillar, SnAg, micro-bumps) and substrate pad finishes for robust interconnect performance.
• Drive package integration from die to substrate, ensuring alignment, coplanarity, and yield optimization.
• Evaluate and mitigate assembly risks including warpage, non-wet opens, voiding, head-in-pillow, and interconnect defects.
• Collaborate with substrate vendors, OSATs, and internal teams to define design rules (pad pitch, bump pitch, keep-outs, stack-ups).
• Lead process development for reflow profiles, flux selection, cleaning, and underfill dispense/cure.
• Perform root cause analysis of assembly and reliability failures using cross-sectioning, SEM, CSAM, and other failure analysis techniques.
• Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling.
• Work cross-functionally with design, reliability, thermal, and manufacturing teams to ensure robust package performance from concept through high-volume production.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed