Package Mechanical FEA Engineer

Cspeed • Palo Alto, CA

3d • Onsite

About The Position

Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware.
Cspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true “scale-up” architectures. Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures.
The Role
This position owns structural finite element analysis for CspeedIO optical engine packages: warpage prediction through the assembly process, stress in bump and interconnect structures, and the lifetime models supporting qualification.
The mechanical problem here is constrained twice. As in any advanced package, expansion mismatch across a heterogeneous stack drives warpage, interconnect stress, dielectric cracking, and delamination. In addition, warpage is an optical constraint — out-of-plane deformation displaces optical facets and coupling features, so a package that is mechanically sound can still fail optically. Acceptance criteria are therefore set by optical coupling as well as by reliability.

Requirements

• MS or PhD in Mechanical Engineering, Materials Science, Engineering Mechanics, or equivalent practical background.
• 6+ years of structural FEA for semiconductor packaging, including warpage and interconnect stress analysis on a product carried into build.
• Deep hands-on capability in Ansys Mechanical, Abaqus, or equivalent, including nonlinear material modeling.
• Command of nonlinear and time-dependent material behavior — creep, viscoplasticity, viscoelasticity, fatigue — with correct treatment of temperature and rate dependence.
• Working knowledge of solder constitutive models and fatigue life prediction methods.
• Demonstrated correlation against physical measurement, and the judgment to distinguish a modeling error from a process excursion.

Nice To Haves

• Chip-package interaction analysis including back-end-of-line and low-k dielectric stress.
• Board-level reliability and PCB-to-package interaction modeling; JEDEC and IPC qualification methodology.
• Photonic or optoelectronic packaging, particularly warpage as an optical alignment constraint or stress effects on optical behavior.
• Coupled thermal-structural workflows, including transfer of a computed temperature field into a structural model.
• Design of experiments and surrogate modeling to compress large parametric studies.

Responsibilities

• Predict warpage at each stage of the assembly process — bonding, reflow, underfill cure, encapsulation, lid attach, singulation — using process-sequential modeling rather than end-state analysis alone, including viscoelastic and cure-shrinkage behavior.
• Own the flatness, coplanarity, and facet planarity budgets that assembly and optical coupling depend on.
• Analyze stress and strain in micro-bump, copper pillar, C4, and second-level interconnect structures, including chip-package interaction and low-k dielectric risk.
• Own solder and interconnect fatigue life prediction, and model thermal cycling, shock, drop, and board-level reliability against JEDEC and IPC methodology.
• Quantify stress in the photonic IC and its consequences for optical performance, in partnership with the photonic design team.
• Define simulation methodology and modeling standards with documented, auditable assumptions, and correlate predictions against measured warpage, cross-section, and reliability data.
• Provide design guidance and sign-off criteria during architecture definition — stack-up, thickness, bump pitch, underfill and stiffener selection — rather than after design freeze.
• Engage substrate suppliers and OSATs on process assumptions, measured warpage data, and material characterization.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior