Package Design Engineer

TYLsemi • San Jose, CA

15h • $180,000 - $216,000

About The Position

TYLsemi is seeking a Package Design Engineer to own design of IC packages (flip-chip, wirebond and 2.5D/interposer platforms) for high-speed digital and data-center-class products. The successful candidate will drive package design from bump/ball map definition through substrate stack-up, routing, signal/power integrity closure, and tapeout — working closely with SI/PI, silicon design, and test engineering to deliver package designs that are robust against real silicon feedback.

Requirements

• Proficiency in Cadence Allegro Package Designer (APD) and associated package layout tools (bump/ball map planning, substrate routing, stack-up definition) for flip-chip/wirebond packaging.
• Demonstrated ability to close package designs against SIPI (signal integrity / power integrity) feedback loops — iterating stack-up, routing, and PDN design based on simulation and/or lab correlation results.
• Solid fundamentals in high-speed digital signal integrity (impedance control, length matching, via stub effects) and power delivery network design.
• Bachelor's or Master's degree in Electrical/Mechanical/Electronics Engineering, or related field.
• Strong analytical and problem-solving skills
• Effective cross-functional communicator, able to work with silicon design, SI/PI, test engineering, mechanical/reliability, and external substrate vendors.

Nice To Haves

• Typically, 5+ years of relevant experience in IC package design
• Working knowledge of package-level SI/PI, thermal, and mechanical issues.
• Experience with Cadence SKILL or equivalent tool for design automation.
• Experience with 2.5D interposer design using Cadence Innovus/Integrity (or equivalent) for silicon interposer / RDL routing.
• Proficiency in Cadence Sigrity/Ansys HFSS/Keysight ADS for package level extraction/analysis of package/interconnect structures.
• Proficiency in Ansys IcePack/Cadence Celsius for package thermal simulation.
• Experience with advanced packaging, Cu Pillar bump technology, and fine-pitch UBM design.
• Working proficiency in Cadence PCB design tools (Allegro X/ PCB Editor / Design Entry HDL) for board-level layout and package-board co-design.
• Familiarity with JEDEC package reliability qualification standards and package-level thermal/mechanical simulation.
• Bonus tools: Cadence Allegro PCB, Cadence Sigrity (PowerDC, PowerSI), Ansys HFSS , Cadence Innovus (2.5D interposer), Keysight ADS.

Responsibilities

• Own end-to-end package design in Cadence Allegro Package Designer (APD) for design feasibility studies through tapeout: bump/UBM mapping, ball map planning, substrate stack-up definition, and fan-out/escape routing.
• Route and close high-speed signal nets (e.g. Parallel interfaces such as UCIe, LPDDR/DDR; SerDes interfaces such as PCIe, Ethernet and UFS) using controlled-impedance and length-matching techniques.
• Design and optimize power delivery networks (PDN) for IC package, including plane splits, decoupling strategy, and via stitching.
• Partner with SI/PI engineering - use SIPI feedback to iterate and harden the package design.
• Drive DRC/DFM closure with substrate vendors; manage design review cycles through tapeout.
• Collaborate cross-functionally with mechanical/thermal/reliability engineering on warpage, CTE mismatch, and underfill selection for package robustness.
• Document design decisions, stack-up specifications, and via schedules for design reuse and knowledge transfer.

Benefits

• The compensation range shown below represents total target cash compensation and includes both base salary and target bonus. Actual compensation will vary based on factors such as experience, skills, qualifications, job level, and work location.
• In addition to cash compensation, this position is eligible for equity in the form of stock options, giving you the opportunity to share in the Company’s long-term growth and success.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior