Package Design Engineer - Signal and Power Integrity (TERADYNE, North Reading, MA)

Teradyne•North Reading, MA

1d•$111,300 - $178,200•Onsite

About The Position

Teradyne is seeking a Package Design Engineer with an electrical engineering foundation and developing experience in signal integrity, power integrity, package design, or high-speed hardware development to support advanced measurement ASIC products within the Semiconductor Test Division. This role contributes to the physical realization of complex RF, analog, digital, and mixed-signal ASIC products across the chip, package, board, socket, fixture, and system interconnect environment. Working under limited direction and in collaboration with experienced package, SI/PI, thermal, mechanical, ASIC, PCB, manufacturing, and supplier teams, the Package Design Engineer will independently develop analysis approaches for assigned work, provide practical solutions to difficult package design problems, and contribute to design decisions whose accuracy can materially affect project cost and schedule.

Requirements

Bachelor of Science in Electrical Engineering (BSEE) or a closely related electrical engineering discipline required.
Two or more years of relevant engineering experience in semiconductor packaging, high-speed digital or mixed-signal hardware, signal integrity, power integrity, PCB design, package design, modeling, validation, or a related field.
Working knowledge of electromagnetic field and transmission-line fundamentals, impedance control, reflections, crosstalk, return paths, high-speed signaling, and power-distribution concepts.
Experience or coursework using time-domain and frequency-domain analysis methods, S-parameters, circuit simulation, or electromagnetic field solvers.
Familiarity with package and PCB design concepts, fabrication, assembly, and design-for-manufacture considerations.
Strong analytical, diagnostic, organizational, written communication, and presentation skills.

Nice To Haves

Experience with Cadence tools preferred; experience with Ansys, HyperLynx, ADS, HFSS, SPICE, or comparable tools is also relevant.
Familiarity with IBIS, IBIS-AMI, or SPICE-class models preferred.
Experience using laboratory equipment such as a VNA, TDR/TDT, or high-speed oscilloscope preferred.
Programming or automation experience with Python, Tcl, MATLAB, Perl, C/C++, C#, Visual Basic, or similar tools is preferred.

Responsibilities

Support ASIC package signal and power integrity development, including package stackup evaluation, bump and BGA escape planning, return-path control, power-delivery partitioning, and package-to-board co-design.
Develop and review package and PCB layout constraints for high-speed serial links, clocks, DUT I/O, power rails, and sensitive analog or mixed-signal interfaces while balancing electrical performance, manufacturability, reliability, cost, and schedule.
Apply electromagnetic and transmission-line principles to evaluate package, board, socket, connector, interposer, and fixture interconnects in the time and frequency domains.
Build, review, and document simulation models for insertion loss, return loss, crosstalk, mode conversion, skew, impedance discontinuities, resonances, eye behavior, and power-distribution performance.
Support package-level power-distribution-network analysis, including target impedance, decoupling strategy, DC IR drop, current density, transient droop or noise, and plane or cavity resonance.
Participate in thermal and mechanical co-design reviews addressing heat-flow paths, material and stackup choices, thermal-interface materials, package warpage and coplanarity, CTE interaction, stress, attachment methods, and package-to-board interfaces.
Collaborate with ASIC design, PCB design, thermal, mechanical, test, characterization, manufacturing, procurement, quality, EDA tool teams, and external package and PCB suppliers to identify and close assigned technical risks.
Contribute to design-for-manufacture and design-for-assembly reviews for package substrates and PCBs.
Plan and support simulation-to-hardware correlation using S-parameters, VNA, TDR/TDT, high-speed oscilloscopes, probes, fixtures, and coupon structures under guidance from senior engineers.
Prepare clear design-review materials, analysis summaries, requirements, constraints, model documentation, and action-item closure evidence.