NoC Interconnect Design Engineer and Architect
About The Position
The NoC bus team group consists of a multi-disciplinary group involved from early product specification and analysis effort to final RTL delivery to the SoCs. One aspect of the process is to identify architecture bottlenecks and drive micro-architecture choices using performance and power analysis, and to provide the SoC team with design guidelines for bus protocol compliance and best power interconnect. Candidates should have strong knowledge of bus protocols, synthesis tools, process nodes, VLSI design, and successful industry experience with deployment of IPs in large SoC projects while working in a collaborative environment.
Requirements
- Knowledge of various bus protocols (AHB, AXI, CHI, …), network on chip
- Strong working knowledge of architecture tradeoff analysis
- Strong knowledge of ASIC flow (synthesis, STA, Lint), power tools
- Skills for trouble shooting and problem solving, including RTL design, FPGA and post-silicon debug
- Ability to define bus components micro-architecture with knowledge of performance/power/area tradeoff
- Ability to quickly react and adapt to changes
- Excellent communication skills
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field.
Nice To Haves
- Familiarity with CPU architecture is a big plus.
Responsibilities
- Creating micro-architecture bus components specifications
- Analyzing the performance results
- Deliver RTL and run tool flows
- Evaluating new IPs
- Driving new protocol deployments
- Defining system wide guidelines for IPs to inter-operate together in the SoC
- Deliver RTL to the SoC team
- Support verification and silicon validation teams
- Work with SW teams to support successful deployments of the interconnects
Benefits
- competitive annual discretionary bonus program
- opportunity for annual RSU grants
- highly competitive benefits package
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
