Next Gen, High-Speed, Memory and Cache Controller Design Engineer
About The Position
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Next Generation, High-Speed, Memory and Cache Controller Design Team is looking for a Senior ASIC Design Engineers for the next generation high speed HBM/LPDDR/DDR memory controller. The front end of the DDR controller interfaces to the rest of the system such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1Ghz+) designs in QCT products. The candidate will work on architecture, design (RTL coding), and deployment of the next generation, high-speed memory systems into QCT products. You will develop or contribute to the development of architecture and design specifications and drive the micro-architecture of portions of the logic design. You will implement and deliver RTL and work with verification engineers to deliver high quality designs. You will be responsible for debugging your designs and also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to be key tasks. You will make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.
Requirements
- Bachelor's degree in Science, Engineering, or related field.
- Experience with LPDDR memory and cache controller, NoC based architectures especially the front end interfacing to the CPU, DSP, and multimedia processors
- Experience with x86 or ARM CPU/bus architectures
- Experience with ordering of memory transactions and methods to enforce proper ordering in order to conform to ISA architecture specification
Nice To Haves
- Exposure to HBM memory type designs
- On-chip tightly coupled SRAM & L3 cache controller architecture/design
Responsibilities
- Define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products.
- Collaborate with cross-functional groups to determine product execution path.
- Work on architecture, design (RTL coding), and deployment of the next generation, high-speed memory systems into QCT products.
- Develop or contribute to the development of architecture and design specifications and drive the micro-architecture of portions of the logic design.
- Implement and deliver RTL and work with verification engineers to deliver high quality designs.
- Responsible for debugging your designs and also provide debug support when integrated into the rest of the chip.
- Perform Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis.
- Make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.
Benefits
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Highly competitive benefits package designed to support your success at work, at home, and at play.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Entry Level
