Next-Gen, High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm•San Diego, CA

32d•$140,000 - $210,000

About The Position

Next Generation, High-Speed, Memory and Cache Controller Design Team is looking for a Senior ASIC Design Engineers for the next generation high speed HBM/LPDDR/DDR memory controller. The front end of the DDR controller interfaces to the rest of the system such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1Ghz+) designs in QCT products. The candidate will work on architecture, design (RTL coding), and deployment of the next generation, high-speed memory systems into QCT products. You will develop or contribute to the development of architecture and design specifications and drive the micro-architecture of portions of the logic design. You will implement and deliver RTL and work with verification engineers to deliver high quality designs. You will be responsible for debugging your designs and also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to be key tasks. You will make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.

Requirements

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Bachelor's or Masters degree in Science, Engineering, or related field.
5+ years ASIC design, RTL coding, front-end digital design experience
3+ years Hardware Architecture experience

Nice To Haves

3-10 years of ASIC design (RTL coding) Preferred
Exposure to RTL Design Verification flows is a plus
3+ years of direct Hardware Architecture experience
Bachelors degree in Electrical or Computer Engineering and at least 5+ years of experience in high speed digital design
Master's degree preferred
Experience with LPDDR memory and cache controller
Experience with NoC based architectures especially the front end interfacing to the CPU, DSP, and multimedia processors
Exposure to HBM memory type designs
On-chip tightly coupled SRAM & L3 cache controller architecture/design
Experience with x86 or ARM CPU/bus architectures
Ordering of memory transactions and methods to enforce proper ordering in order to conform to ISA architecture specification

Responsibilities

Architecture, design (RTL coding), and deployment of the next generation, high-speed memory systems into QCT products.
Develop or contribute to the development of architecture and design specifications.
Drive the micro-architecture of portions of the logic design.
Implement and deliver RTL.
Work with verification engineers to deliver high quality designs.
Debugging designs and provide debug support when integrated into the rest of the chip.
Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis.
Make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.