New Graduate Engineer, Silicon Engineering
About The Position
SpaceX is looking for engineers graduating in fall or this upcoming spring/summer for full-time employment after graduation to help develop next generation silicon for SpaceX. The team is hiring engineers from pre-silicon through post-silicon across many disciplines in RF/Analog IC, RTL design, design verification, physical design, DFT, validation and more using state-of-the-art tools and methodologies. The ideal candidate will be a hands-on self-starter who can execute the steps required to fully design and verify complex designs. Full-time employment is available working on our Starlink program in Palo Alto (CA), Irvine (CA), or Redmond (WA).
Requirements
- Graduating with a bachelor’s degree, master’s degree or PhD in 2026 or 2027
- Bachelor’s degree in an engineering discipline, mathematics or physics
- Experience working with ASIC, SOC, FPGA, RFIC, or MMIC
Nice To Haves
- Understanding of computer architecture
- Analog or digital CMOS integrated circuit design and/or physical design
- SystemVerilog, Verilog, VHDL or C/C++
- Scripting languages, e.g. Python for automation
- Object-oriented programming
- Simulation tools such as ADS, Spectre, HFSS or Momentum
- RTL design, chip bring-up, verification, and/or post-silicon validation experience
- Digital signal processing
Responsibilities
- Participate in all phases of ASIC/FPGA design and verification flows
- Contribute towards design architecture, RTL implementation and/or verification, and emulation
- Bring-up and validate ASICs and FPGAs in the lab (write embedded software using C/C++ and/or Python)
- Hands-on self-starter who can execute the steps required to fully verify a complex digital design
- Simulate and model RFIC systems at high level and work with system architects, modem/DSP and ASIC engineers to partition functions between hardware and software domains
- Derive specifications for the RFIC subsystems and circuits
- Develop RF/microwave circuits in state-of-the-art SiGe or CMOS processes
- Perform IC floor planning and layout
- Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer, error correction, etc.)
- Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers
- Perform synthesis and physical implementation steps (synthesis, floor planning, place and route, timing/noise analysis, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
- Develop/improve physical design methodologies and automation scripts for various implementation steps
- Participate in silicon tapeouts in advanced technology nodes for future Starlink SOCs
Benefits
- Company stock or long-term cash awards
- Potential discretionary bonuses
- Employee Stock Purchase Plan
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- Short and long-term disability insurance
- Life insurance
- Paid parental leave
- Various other discounts and perks
- 3 weeks of paid vacation
- 10 or more paid holidays per year
- Paid sick time (in Washington State)
- Company shuttles (from select Seattle locations to Redmond office)
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
