Neuromorphic Front-End Silicon Lead

Intel Corporation•Austin, TX

7d•$220,920 - $311,890•Hybrid

About The Position

For nearly a decade, Intel's Neuromorphic Computing Lab has explored architectures, algorithms, and software inspired by the brain's efficiency, scalability, and adaptability. Our Loihi series of research chips pioneered event-driven, sparse, and massively parallel neuro-inspired processing. Now, we're entering a new chapter: transforming these breakthroughs into real-world products that will power the coming era of physical AI systems. This principal-level role calls for a talented technical leader with a track record of realizing new processor and accelerator architectures, plus strong SoC integration experience including high-speed interfaces such as Ethernet, PCIe/UCIe, and memory controllers. Your multidisciplinary team will turn emerging neuromorphic and AI accelerator concepts into robust, manufacturable silicon. First-principles thinking and an openness to learning new technologies and methodologies, such as asynchronous design and AI automation, are essential.

Requirements

MS in Electrical/Computer Engineering, Computer Science, or a related field.
10+ years of hands-on design experience in processors, accelerators, SoCs, or custom ASICs.
5+ years of experience with RTL design (Verilog/SystemVerilog) and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV).
3+ years leading silicon design and/or verification teams.

Nice To Haves

PhD with a research background in hardware acceleration, especially AI.
Experience with advanced packaging and heterogeneous integration technologies (e.g., chiplets, UCIe, 2.5D/3D).
Experience with asynchronous design methods and custom memory/circuit co-design.
Experience with pre-silicon enablement via emulation or FPGA prototyping.
Experience with low-power (UPF) methods and security features such as Root of Trust and secure boot.
History of technical ownership on multiple product tape-outs.

Responsibilities

Engage with architects and AI researchers to identify hardware innovations and optimizations, and translate them into implementable microarchitectures.
Lead a team responsible for design implementation and verification through post-silicon validation.
Partner with physical/custom design engineers, often first prototyping blocks through place-and-route prior to hand-off, and co-design critical custom circuits such as memories to achieve the best KPIs.
Evaluate, select, and integrate internal and external IP, including I/O interfaces.
Work with software and systems teams to enable development long before tape-out and ensure smooth post-silicon bring-up.
Mentor engineers and strengthen design and verification practices as the program scales.