MTS Silicon Design Engineer

Advanced Micro Devices, Inc•Austin, TX

5d•Onsite

About The Position

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

Requirements

Master’s degree or foreign equivalent in Electronics Engineering, Computer Engineering, Electrical Engineering or related field.
Three (3) years of experience in the job offered or a closely related engineering role.
IP level ASIC verification
Debugging firmware and RTL code using simulation tools
Verilog, System Verilog, C, and C++
Automating workflows in a distributed compute environment
Scripting languages such as Perl, Ruby, Makefile, or shell
Siemens Tessent tool experience for scan insertion and iJTAG
MBIST with Siemens or Synopsys SMS
Scan insertion, ATPG, iJTAG, clock distribution, voltage, and power aware topology planning.

Responsibilities

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
Estimate the time required to write the new feature tests and any required changes to the test environment.
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
Plan and implement RTL features for the product lifecycle of AMD Instinct products, reduce overall test and debug costs and increase overall yield of silicon.