We are seeking a Mixed-Signal Verification Engineer III to verify analog and mixed-signal IP integrated into digital-on-top SoC environments on the Treo platform. This mid-level individual contributor role reports directly to the Analog Design Team Manager. You will own the development and execution of mixed-signal verification solutions, leveraging SystemVerilog and behavioral modeling to ensure power and clock IP meet functional and integration requirements prior to tape-out.
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Job Type
Full-time
Career Level
Mid Level
Education Level
No Education Listed