Mixed-signal Design Architect, HBM Architecture

Micron Technology • Folsom, CA

5d • $146,000 - $297,000 • Onsite

About The Position

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence. This role is within Micron's High Bandwidth Memory Architecture organization, which partners closely with customers to deliver memory solutions purpose-built for emerging AI systems and applications. As a Senior Engineer, Principal Engineer, or Member of Technical Staff, Design Architect in the Next-generation HBM Architecture Team, you will design, simulate, analyze, and optimize the architecture of 3D-stacked, high-performance memories. You will apply your knowledge to explore trade-offs in 3D-stacked logic and memory designs in close collaboration with peer architecture and design teams. Your responsibilities will include definition of, evaluation of, and specification of circuit implementations, technology requirements, thermal performance improvements, power delivery architectures, and on- and off-chip interfaces.

Requirements

• Experience with analog and/or mixed-signal design, including simulation and floorplanning.
• Experience with transistor-level simulation (e.g., FineSim, HSPICE) including corner analysis.
• Ability to analyze architecture tradeoffs and use findings to develop specifications.
• Experience with power delivery analysis, tradeoffs, constraints, and challenges.

Nice To Haves

• Familiarity with DRAM or high-performance, 3D-stacked memory devices like HBM.
• Contributions to thermal and/or power delivery solutions for stacked architectures.
• Experience in one or more scripting languages (e.g., Python, Perl) and hardware description language (e.g., Verilog).
• A Masters or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
• 5+ years of proven experience delivering mixed-signal circuit designs, 3D-stacked memory or logic designs, or complex packaging architectures.

Responsibilities

• Design, optimize, and simulate critical analog and/or mixed-signal circuits.
• Architect and design power delivery for high-performance, stacked memories.
• Analyze, specify, and prototype on-/off-chip interfaces.
• Perform timing, area, power, and complexity analysis for high-performance, low-power circuits.
• Define architectures for improved thermal management.
• Conduct pathfinding activities for future-generation stacked-memory products.
• Compose and maintain clear architecture documentation.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Senior