Mixed Signal Custom Layout Engineer (1-Year Temporary)

Advanced Micro Devices, Inc•Markham, ON

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The full custom IC layout group is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry leading CAD tools and cutting edge foundry technology. Examples of layout designed by our team include Phase Locked Loop (PLL), Delay Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High Speed Differential Signaling circuitry, Droop Detect, and Die Crack Monitor. Proficiency in 2D layout design while being able to visualize in 3D space are traits ideal for this position. It is useful to have knowledge of digital and analog circuitry at the CMOS transistor level. The candidate will be able to see through the different stages of a project development – from initial floor planning and routing of low level logic gates through top level integration of numerous blocks and ultimately, project tape out related tasks. Day to day responsibilities include layout of lower level cells and assembly of these lower level cells into IPs. You will be running various verification tools at all levels of the design hierarchy. These include DRC, LVS, EM/IR, ERC and Latch up/ESD. Over time, responsibilities will expand to include guiding and coordinating off‑shore contractors performing layout tasks.

Requirements

Proficiency in 2D layout design while being able to visualize in 3D space.
Knowledge of digital and analog circuitry at the CMOS transistor level.
Ability to see through the different stages of a project development – from initial floor planning and routing of low level logic gates through top level integration of numerous blocks and ultimately, project tape out related tasks.
Running various verification tools at all levels of the design hierarchy: DRC, LVS, EM/IR, ERC and Latch up/ESD.

Nice To Haves

Strong understanding of CMOS device/circuit theory and analog/digital layout best practices.
Custom layout using Cadence Virtuoso.
Physical verification using Mentor/Siemens Calibre (LVS, DRC, PERC) and ERC/EM/IR flows.
Scripting/automation in Perl, TCL, SVRF/TVF, SKILL is a plus.
Exposure to advanced nodes (e.g., 2nm/3nm; experience at 5nm/7nm also valued).
Background with IP/standard-cell layout, high-speed differential signaling, PLL/DLL/VCO, DACs, power pads, and in-context XOR.

Responsibilities

Create clean, robust layouts for digital and analog building blocks at the transistor level in Cadence Virtuoso.
Floorplan, route, and assemble lower-level cells into macros
Build black-box/abstract models and views consumed by other teams; contribute to tapeout collateral for custom blocks.
Run hierarchical checks at cell/macro levels (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and iterate to closure in partnership with circuit owners.
Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality.
Guiding and coordinating off‑shore contractors performing layout tasks.