Micro-Architect and RTL Designer
About The Position
MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.
Requirements
- Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon
- 4 years or more experience with SystemVerilog, Python, C/C++ and similar scripting and programming languages for chip design and related flows
- Production-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management and related functionalities
- Experience with testing your designs and working closely with verification teams towards performance and coverage closure goals
- Hands-on experience with design synthesis, design lint, and related flows to take designs to high quality sign-off
Nice To Haves
- Familiarity with verification, emulation platforms and methodologies is a plus
- Experience with high speed I/O IP is a plus
- A lot of experience with logic that focuses on moving, storing, or managing data such as caches, buffers, crossbars, etc… is a plus
Responsibilities
- Contribute to MatX’s silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, fullchip design
- Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design
- Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards various silicon milestones including design freeze and tapeout
- Work closely with the verification, DFT, and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results
Benefits
- Company subsidized Health, Dental, Vision, and Life insurance
- Pre-tax Health Savings Accounts with generous company contribution
- 4 weeks paid time off (accrued)
- 12 company holidays
- Up to 12 weeks of paid parental leave, regardless of your path to parenthood
- $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities
- Team Lunches, quarterly off-sites, and regular town halls
- 401K and/or Roth IRA, with 5% company contribution
- Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expenses
- Commute On Us For those commuting up to 1 hour, put your rideshare cost on our company card and reclaim the drive-time to get work done!
- $50 per month to use on the perks you care about most
- Home-tech setup
- Remote wifi expense reimbursement
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
Education Level
No Education Listed
