Memory System Designer and Place and Route Engineer

Broadcom • Mendota Heights, MN

6d • $108,000 - $172,800

About The Position

We are looking for an energetic and passionate design engineer to join our Central Engineering Group and be part of a memory subsystem design team responsible for the development of large memory blocks and subsystems. Typically requires a minimum of 8 years of relevant experience and a Bachelor in Electrical Engineering.

Requirements

• Strong design skills
• Ability to write and debug Verilog RTL code
• Place and route expertise
• Proficient in running STA, DRC, EM/IR tools, and attaining design closure
• Ability to code in Python
• Good understanding of synthesis tools and running synthesis
• Capable of running and debugging logical equivalency checkers
• Familiar with memory behavior
• Proficient in writing automation scripts, and tools savvy
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven, and good at multitasking
• Minimum of 8 years of relevant experience
• Bachelor in Electrical Engineering

Responsibilities

• Architect and design memory subsystems
• Implement RTL of subsystem designs
• Place and route (physical design)
• Design closure: timing, DRC, LVS, EM/IR, etc.
• Gate netlist synthesis

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave
• vacation time
• Paid Family Leave
• other leaves of absence

What This Job Offers

• Job Type: Full-time
• Career Level: Senior