Memory Subsystem Enablement Verification Engineer

Advanced Micro Devices, Inc•Ottawa, ON

1d•Hybrid

About The Position

The Memory Subsystem team is looking for passionate and experienced pre-silicon Verification engineers for the pre-silicon readiness of high-speed LPDDRx, DDRx and associated IPs through the utilization of advanced co-simulation hybrid environments. The individual will be part of a high performing team that focuses on all things DDR to shift left productization. Be a part of the definition, design, and development phase of industry-leading memory subsystem end to end solution.

Requirements

Excellent knowledge of C, C++, System Verilog
Experience in ground-up development and verification with IP and Subsystem verification
Advanced testbench architecture, microarchitecture, development, and implementation experience, including co-verification
In depth knowledge of code and functional coverage constructs as well as test plans to coverage relationships
Development and debug of co-verification environment with production level firmware
Development and maintenance of test suite through firmware feature set modification as well as custom transactor-based stimulus development
Subsystem and block level test plan development in relationship to FW/HW co-verification and maintenance as well as subsystem test plan development
Ability to adapt and learn new toolsets and framework, making updates as needed

Nice To Haves

Knowledge and development of monitors and checkers and/or experience developing SVA/OVL and synthesizable assertions
Experience with DDR/JEDEC standard IP, DDR PHY, or Memory Controller verification.
UVM object-oriented design
Understanding and experience utilizing architectural models
Knowledge of System C and Python
Zebu Emulation verification and debug experience
Experience in hardware/Firmware co-verification in UVM System Verilog, C-DPI, and gasket structured testbench
Memory VIP integration, initialization, and debug experience
End to end verification experience from front end verification through lab bring up
Strong understanding of synchronization techniques (handshakes, message passing); knowledge of hardware level clocking and multi-domain simulation synchronization
Strong knowledge of GIT and perforce
Development and maintenance of regressions as well as coverage databases.
SoC IP knowledge and architectural understanding of the purpose of each IP

Responsibilities

Excellent knowledge of C, C++, System Verilog
Experience in ground-up development and verification with IP and Subsystem verification
Advanced testbench architecture, microarchitecture, development, and implementation experience, including co-verification
In depth knowledge of code and functional coverage constructs as well as test plans to coverage relationships
Development and debug of co-verification environment with production level firmware
Development and maintenance of test suite through firmware feature set modification as well as custom transactor-based stimulus development
Subsystem and block level test plan development in relationship to FW/HW co-verification and maintenance as well as subsystem test plan development
Ability to adapt and learn new toolsets and framework, making updates as needed