TD Memory Quality and Reliability Engineer

Intel•Folsom, CA

9d•Hybrid

About The Position

The Technology Development (TD) Quality and Reliability organization enables successful deployment of Intel's leading-edge process technologies through silicon-based quality, reliability, and technology readiness assessments. The Memory Quality and Reliability team partners with Design, Device Engineering, Product Development Engineering, and Yield organizations to develop, characterize and certify SRAM, Register File (RF), and Fuse array for advanced technology nodes. The team supports technology certification and PDK release milestones by establishing certification strategies, developing certification methodologies, performing silicon characterization, generating predictive Vccmin models, and assessing product risk for internal and external customers. We are seeking an experienced Memory Quality and Reliability Engineer to drive post-silicon memory characterization, certification, and technology readiness activities for advanced SRAM, Register File (RF) and/or fuse array. In this role, you will help improving certification methodologies, analyzing large-scale silicon characterization data, developing Vccmin/Vmax predictive models, assessing silicon-to-simulation correlation (Sil2Sim), and providing risk assessments that guide technology development, product deployment, and PDK release decisions. You will work with design, device, process, test, and yield organizations to transform silicon learning into certification decisions and actionable technology improvements.

Requirements

Ph.D. in Electrical Engineering, Computer Engineering, Physics or related discipline with 2+ years of semiconductor industry experience OR M.S. in Electrical Engineering, Computer Engineering, Physics, Materials Science, or related discipline with 6+ years of semiconductor industry experience.
2+ years of hands-on experience with memory testing.
2+ years of experience performing quantitative analysis of large-scale memory or semiconductor datasets using statistical methods such as DOE, SPC, regression analysis, hypothesis testing, or multivariate analysis.
2+ years of hands-on experience using JMP and Python for data analysis, statistical modeling, process optimization, automation, or data visualization.

Nice To Haves

Experience in memory design, characterization, validation, modeling, product development, quality, reliability, or technology development.
Strong understanding of SRAM and/or Register File design fundamentals, silicon characterization techniques, and variability analysis.
Experience developing silicon-based predictive models, statistical distributions, guardbands, and product risk projections.
Knowledge of Vmin/Vmax characterization methodologies, memory margin assessment, array screening techniques, or design technology co-optimization.
Experience with silicon-to-simulation correlation (Sil2Sim), SPICE modeling, or design validation.
Familiarity with technology certification, PDK development, or product deployment processes.
Programming experience in Python, JSL, SQL, or data analytics frameworks.

Responsibilities

Plan and execute SRAM, RF, and/or Fuse technology certification supporting technology development and certification milestones.
Define and maintain certification methodologies and criteria, test strategies, and readiness requirements for memory array.
Drive memory array characterization across multiple operating conditions to evaluate Vmin, Vmax, aging behavior, variability, and design margins.
Analyze silicon characterization data to identify performance gaps, failure signatures, systematic trends, and technology risks.
Develop, validate, and maintain silicon-based Vccmin and Vmax predictive models used for technology certification, PDK releases, and product guidance.
Perform silicon-to-simulation (Sil2Sim) correlation assessments and drive understanding of discrepancies between measured silicon behavior and design predictions.
Collaborate with Yield, Design, Device Engineering, PDE, Defect Rel and FIFA teams to define root-cause hypotheses, resolution paths, and technology improvement recommendations on meeting technology commit for memory offers.
Generate certification reports, readiness assessments, and risk projections that support technology deployment decisions.
Present technical findings and recommendations to engineering leadership, program teams, and customers.
Drive continuous improvement of memory certification methodologies, modeling approaches, characterization flows, and data analytics infrastructure.
Provide technical mentorship and leadership within a highly collaborative cross-functional environment.