Member of Technical Staff - Formal Verification

Architect Labs•Palo Alto, CA

About The Position

Architect is an AI lab for the compute stack, starting with chip design. We build AI systems to design on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads, and enable a new era of domain-specific chips that unlock capabilities impossible with current hardware paradigms. Born out of Stanford Research, our team blends AI with Silicon with a founding team from Anthropic, Google DeepMind, Meta SuperIntelligence, xAI, Apple and Intel. As a Founding Member of the Technical Staff - Formal Methods at Architect Labs, you'll work on the formal foundations of our chip design flow. You will own a critical layer of the stack that gives our system the rigor required to take AI-generated hardware artifacts into verified production-grade silicon. This is fundamental research applied directly to industry-grade chips, with tight feedback loops between theory and tape-out. This is a hands-on, 0→1 role where you'll own the formal stack end-to-end: spec language, IR, proof obligations, solver integration, and the empirical evidence that the whole thing works on real blocks.

Requirements

PhD in Computer Science, EECS, or a closely related field, with a dissertation or equivalent body of work in formal methods applied to hardware or systems. Exceptional candidates with a BS/MS and a strong industrial track record in formal verification will be considered.
Deep expertise in at least two of: temporal logic and model checking, SMT-based verification, refinement-based specification, or proof assistants applied to hardware/distributed/concurrent/low-level systems.
Experience with formal frameworks or proof tools, such as TLA+, Lean, Coq, or similar.
A demonstrated history of applying formal methods to a real artifact that shipped not only published proofs.
Comfortable across the formal stack. You have used multiple tools and have opinions on when each is the right answer; you are not a single-tool maximalist.
Strong software engineering skills. You can build the toolchain, not only specify it. Comfortable with compiler-style infrastructure and integrating formal tools into automated pipelines.
Fast-moving builder who can take a research-grade formal idea and turn it into a production component on a chip-design timeline. You ship.

Nice To Haves

Industrial formal verification experience at leading silicon companies, automated reasoning groups, or specialized formal methods firms.
Experience with design of HLS (High-Level Synthesis) tools.
Background in compiler/IR design or DSL implementation that real engineers used.
Publications at top formal methods, PL, or EDA venues (CAV, FMCAD, POPL, PLDI, TACAS, DAC, ICCAD, DVCon).
Familiarity with modern AI/ML systems and how learned components interact with formal guarantees — not required, but a plus.
Experience as an early technical hire at a deeptech or formal-methods startup.

Responsibilities

Design and implement the formal specification language and intermediate representation that sits at the heart of our flow, across hardware specifications, testbench, assertions and RTL.
Build the proof-obligation generator that emits checkable claims (entailment of assertions from spec, refinement of RTL from spec) and the toolchain that discharges them via SMT solvers, model checkers, and proof assistants as appropriate.
Establish the soundness arguments and coverage-adequacy methodology that let us claim, with evidence, that our generated artifacts faithfully characterize the spec.
Co-design with our verification methodology and ML research teams: your formal layer is the oracle the agent loop optimizes against, and the boundary between "provable" and "tested" is a decision you make and defend.